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Searched refs:lhz (Results 1 – 25 of 62) sorted by relevance

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/external/llvm/test/CodeGen/PowerPC/
Djaggedstructs.ll26 ; CHECK: lhz {{[0-9]+}}, 165(1)
33 ; CHECK: lhz {{[0-9]+}}, 182(1)
38 ; CHECK: lhz {{[0-9]+}}, 189(1)
Dpeephole-align.ll80 ; POWER7-DAG: lhz [[REG0_0:[0-9]+]], h2v@toc@l([[REGSTRUCT]])
81 ; POWER7-DAG: lhz [[REG1_0:[0-9]+]], h2v@toc@l+2([[REGSTRUCT]])
89 ; POWER8-DAG: lhz [[REG0_0:[0-9]+]], 0([[REGSTRUCT]])
90 ; POWER8-DAG: lhz [[REG1_0:[0-9]+]], 2([[REGSTRUCT]])
108 ; CHECK-DAG: lhz [[REG0_0:[0-9]+]], h2v@toc@l([[REGSTRUCT]])
109 ; CHECK-DAG: lhz [[REG1_0:[0-9]+]], h2v@toc@l+2([[REGSTRUCT]])
209 ; POWER7-DAG: lhz [[REG0_0:[0-9]+]], h4v@toc@l([[REGSTRUCT]])
210 ; POWER7-DAG: lhz [[REG1_0:[0-9]+]], h4v@toc@l+2([[REGSTRUCT]])
211 ; POWER7-DAG: lhz [[REG2_0:[0-9]+]], h4v@toc@l+4([[REGSTRUCT]])
212 ; POWER7-DAG: lhz [[REG3_0:[0-9]+]], h4v@toc@l+6([[REGSTRUCT]])
[all …]
Dfast-isel-fold.ll21 ; ELF64: lhz
54 ; ELF64: lhz
90 ; ELF64: lhz
Dunaligned.ll13 ; CHECK: lhz
17 ; CHECK-VSX: lhz
Dbyval-aliased.ll22 ; CHECK: lhz r3, [[OFF]]({{r[3]?1}})
Dvec_extload.ll33 ; Same as v16si8_sext_in_reg, expands to load/store halfwords (lhz/sth).
/external/swiftshader/third_party/llvm-7.0/llvm/test/CodeGen/PowerPC/
Djaggedstructs.ll26 ; CHECK-DAG: lhz {{[0-9]+}}, 165(1)
33 ; CHECK-DAG: lhz {{[0-9]+}}, 182(1)
38 ; CHECK-DAG: lhz {{[0-9]+}}, 189(1)
Dtrunc-srl-load.ll4 ; CHECK-NOT: lhz 4, 4(0)
5 ; CHECK: lhz 4, 2(0)
Dfast-isel-fold.ll21 ; ELF64: lhz
54 ; ELF64: lhz
90 ; ELF64: lhz
Dpeephole-align.ll64 ; CHECK-DAG: lhz [[REG0_0:[0-9]+]], h2v@toc@l([[REGSTRUCT]])
65 ; CHECK-DAG: lhz [[REG1_0:[0-9]+]], h2v@toc@l+2([[REGSTRUCT]])
84 ; CHECK-DAG: lhz [[REG0_0:[0-9]+]], h2v@toc@l([[REGSTRUCT]])
85 ; CHECK-DAG: lhz [[REG1_0:[0-9]+]], h2v@toc@l+2([[REGSTRUCT]])
159 ; CHECK-DAG: lhz [[REG0_0:[0-9]+]], h4v@toc@l([[REGSTRUCT]])
160 ; CHECK-DAG: lhz [[REG1_0:[0-9]+]], h4v@toc@l+2([[REGSTRUCT]])
161 ; CHECK-DAG: lhz [[REG2_0:[0-9]+]], h4v@toc@l+4([[REGSTRUCT]])
162 ; CHECK-DAG: lhz [[REG3_0:[0-9]+]], h4v@toc@l+6([[REGSTRUCT]])
Dunaligned.ll13 ; CHECK: lhz
17 ; CHECK-VSX: lhz
DPR35812-neg-cmpxchg.ll31 ; CHECK: lhz 3, 46(1)
66 ; CHECK-P7: lhz 3, 46(1)
Duint-to-ppcfp128-crash.ll11 ; CHECK: lhz [[LD:[0-9]+]], 0(3)
Dbyval-aliased.ll22 ; CHECK: lhz r3, [[OFF]]({{r[3]?1}})
DmemCmpUsedInZeroEqualityComparison.ll68 ; CHECK-NEXT: lhz 5, 4(3)
69 ; CHECK-NEXT: lhz 6, 4(4)
Dvec_extload.ll33 ; Same as v16si8_sext_in_reg, expands to load/store halfwords (lhz/sth).
/external/libffi/src/powerpc/
Ddarwin_closure.S193 lhz r3,FFI_TYPE_TYPE(r3) ; type => r3
281 lhz r3,6(r5)
283 lhz r3,2(r5)
383 lhz r0,FFI_TYPE_TYPE(r6) ; OK go the type
Daix_closure.S170 lhz r3, 10(r3) /* load type from return type */
226 lhz r3, 112+6(r1)
343 lhz r3, 6(r3) /* load type from return type */
399 lhz r3, 56+2(r1)
Dppc_closure.S183 lhz %r3,112+0(%r1)
185 lhz %r3,112+2(%r1)
251 lhz %r3,112+0(%r1)
/external/python/cpython2/Modules/_ctypes/libffi/src/powerpc/
Daix_closure.S170 lhz r3, 10(r3) /* load type from return type */
226 lhz r3, 112+6(r1)
343 lhz r3, 6(r3) /* load type from return type */
399 lhz r3, 56+2(r1)
Ddarwin_closure.S193 lhz r3,FFI_TYPE_TYPE(r3) ; type => r3
281 lhz r3,6(r5)
283 lhz r3,2(r5)
383 lhz r0,FFI_TYPE_TYPE(r6) ; OK go the type
Dppc_closure.S183 lhz %r3,112+0(%r1)
185 lhz %r3,112+2(%r1)
251 lhz %r3,112+0(%r1)
/external/v8/src/debug/ppc/
Ddebug-ppc.cc41 __ lhz(r3, in GenerateFrameDropperTrampoline() local
/external/capstone/suite/MC/PowerPC/
Dppc64-encoding.s.cs25 0xa0,0x44,0x00,0x80 = lhz 2, 128(4)
/external/v8/src/regexp/ppc/
Dregexp-macro-assembler-ppc.cc432 __ lhz(r6, MemOperand(r3)); in CheckNotBackReference() local
434 __ lhz(r25, MemOperand(r5)); in CheckNotBackReference() local
1325 __ lhz(current_character(), MemOperand(current_character())); in LoadCurrentCharacterUnchecked() local
1336 __ lhz(current_character(), MemOperand(current_character())); in LoadCurrentCharacterUnchecked() local
1356 __ lhz(current_character(), MemOperand(current_character())); in LoadCurrentCharacterUnchecked() local

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