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Searched refs:lvx (Results 1 – 25 of 73) sorted by relevance

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/external/boringssl/linux-ppc64le/crypto/aes/
Daesp8-ppc.S51 lvx 1,0,3
56 lvx 2,0,3
58 lvx 4,0,6
60 lvx 5,8,6
69 lvx 10,0,5
98 lvx 4,0,6
145 lvx 6,0,3
220 lvx 6,0,3
271 lvx 2,0,3
342 lvx 0,0,3
[all …]
/external/boringssl/linux-ppc64le/crypto/fipsmodule/
Daesp8-ppc.S65 lvx 1,0,3
70 lvx 2,0,3
72 lvx 4,0,6
74 lvx 5,8,6
83 lvx 10,0,5
112 lvx 4,0,6
159 lvx 6,0,3
234 lvx 6,0,3
285 lvx 2,0,3
362 lvx 0,0,3
[all …]
Dghashp8-ppc.S554 lvx 20,10,1
556 lvx 21,11,1
558 lvx 22,10,1
560 lvx 23,11,1
562 lvx 24,10,1
564 lvx 25,11,1
566 lvx 26,10,1
568 lvx 27,11,1
570 lvx 28,10,1
572 lvx 29,11,1
[all …]
/external/linux-kselftest/tools/testing/selftests/powerpc/include/
Dvmx_asm.h38 lvx v20,reg,%r1; \
40 lvx v21,reg,%r1; \
42 lvx v22,reg,%r1; \
44 lvx v23,reg,%r1; \
46 lvx v24,reg,%r1; \
48 lvx v25,reg,%r1; \
50 lvx v26,reg,%r1; \
52 lvx v27,reg,%r1; \
54 lvx v28,reg,%r1; \
56 lvx v29,reg,%r1; \
[all …]
/external/boringssl/linux-ppc64le/crypto/modes/
Dghashp8-ppc.S534 lvx 20,10,1
536 lvx 21,11,1
538 lvx 22,10,1
540 lvx 23,11,1
542 lvx 24,10,1
544 lvx 25,11,1
546 lvx 26,10,1
548 lvx 27,11,1
550 lvx 28,10,1
552 lvx 29,11,1
[all …]
/external/linux-kselftest/tools/testing/selftests/powerpc/math/
Dvmx_asm.S15 lvx v0,r5,r4
20 lvx v0,r5,r4
25 lvx v0,r5,r4
30 lvx v0,r5,r4
35 lvx v0,r5,r4
40 lvx v0,r5,r4
45 lvx v0,r5,r4
50 lvx v0,r5,r4
55 lvx v0,r5,r4
60 lvx v0,r5,r4
[all …]
/external/swiftshader/third_party/llvm-7.0/llvm/test/CodeGen/PowerPC/
Dunal-altivec-wint.ll5 declare <4 x i32> @llvm.ppc.altivec.lvx(i8*) #1
11 %vl = call <4 x i32> @llvm.ppc.altivec.lvx(i8* %hv)
21 ; CHECK-DAG: lvx {{[0-9]+}}, 0, 3
22 ; CHECK-DAG: lvx {{[0-9]+}}, 3, [[REG]]
41 ; CHECK-DAG: lvx {{[0-9]+}}, 0, 3
42 ; CHECK-DAG: lvx {{[0-9]+}}, 3, [[REG]]
Dvec_shuffle_le.ll9 ; CHECK: lvx [[REG1:[0-9]+]]
10 ; CHECK: lvx [[REG2:[0-9]+]]
32 ; CHECK: lvx [[REG1:[0-9]+]]
33 ; CHECK: lvx [[REG2:[0-9]+]]
55 ; CHECK: lvx [[REG1:[0-9]+]]
56 ; CHECK: lvx [[REG2:[0-9]+]]
78 ; CHECK: lvx [[REG1:[0-9]+]]
79 ; CHECK: lvx [[REG2:[0-9]+]]
101 ; CHECK: lvx [[REG1:[0-9]+]]
102 ; CHECK: lvx [[REG2:[0-9]+]]
[all …]
Dunal-vec-ldst.ll13 ; CHECK-DAG: lvx [[REG3:[0-9]+]], 3, [[REG1]]
14 ; CHECK-DAG: lvx [[REG4:[0-9]+]], 0, 3
28 ; CHECK-DAG: lvx [[REG4:[0-9]+]], 3, [[REG1]]
29 ; CHECK-DAG: lvx [[REG5:[0-9]+]], 3, [[REG2]]
30 ; CHECK-DAG: lvx [[REG6:[0-9]+]], 0, 3
44 ; CHECK-DAG: lvx [[REG3:[0-9]+]], 3, [[REG1]]
45 ; CHECK-DAG: lvx [[REG4:[0-9]+]], 0, 3
59 ; CHECK-DAG: lvx [[REG4:[0-9]+]], 3, [[REG1]]
60 ; CHECK-DAG: lvx [[REG5:[0-9]+]], 3, [[REG2]]
61 ; CHECK-DAG: lvx [[REG6:[0-9]+]], 0, 3
[all …]
Dbuiltins-ppc-p8vector.ll24 ; CHECK: lvx [[REG1:[0-9]+]], 0, 3
25 ; CHECK: lvx [[REG2:[0-9]+]], 0, 4
39 ; CHECK: lvx [[REG1:[0-9]+]], 0, 3
40 ; CHECK: lvx [[REG2:[0-9]+]], 0, 4
53 ; CHECK: lvx [[REG1:[0-9]+]],
66 ; CHECK: lvx [[REG1:[0-9]+]],
Dvselect-constants.ll20 ; CHECK-NEXT: lvx 4, 0, 4
23 ; CHECK-NEXT: lvx 3, 0, 3
38 ; CHECK-NEXT: lvx 3, 0, 3
39 ; CHECK-NEXT: lvx 4, 0, 4
54 ; CHECK-NEXT: lvx 3, 0, 3
67 ; CHECK-NEXT: lvx 3, 0, 3
85 ; CHECK-NEXT: lvx 3, 0, 3
98 ; CHECK-NEXT: lvx 3, 0, 3
Dunal-altivec.ll33 ; CHECK-DAG: lvx [[CNST:[0-9]+]],
37 ; CHECK-DAG: lvx [[LD1:[0-9]+]], [[B1]], [[C0]]
38 ; CHECK-DAG: lvx [[LD2:[0-9]+]], [[B3]],
Dunal-vec-negarith.ll12 ; CHECK-NOT: v4i32,ch = llvm.ppc.altivec.lvx{{.*}}<(load 31 from %ir.p + 4294967281, align 1)>
13 ; CHECK: v4i32,ch = llvm.ppc.altivec.lvx{{.*}}<(load 31 from %ir.p - 15, align 1)>
Dmem-rr-addr-mode.ll4 ; Codegen lvx (R+16) as t = li 16, lvx t,R
Dppc64-i128-abi.ll80 ; CHECK-NOVSX: lvx [[VAL:[0-9]+]], {{[0-9]+}}, {{[0-9]+}}
94 ; On LE, do not need to swap contents of 2 and 3 because the lvx/stvx
205 ; CHECK-LE: lvx 2, {{[0-9]+}}, {{[0-9]+}}
221 ; CHECK-NOVSX: lvx 2, {{[0-9]+}}, {{[0-9]+}}
234 ; CHECK-LE: lvx 2, {{[0-9]+}}, {{[0-9]+}}
235 ; CHECK-LE: lvx 3, {{[0-9]+}}, {{[0-9]+}}
255 ; CHECK-NOVSX-DAG: lvx 2, {{[0-9]+}}, {{[0-9]+}}
256 ; CHECK-NOVSX-DAG: lvx 3, {{[0-9]+}}, {{[0-9]+}}
/external/llvm/test/CodeGen/PowerPC/
Dunal-altivec-wint.ll5 declare <4 x i32> @llvm.ppc.altivec.lvx(i8*) #1
11 %vl = call <4 x i32> @llvm.ppc.altivec.lvx(i8* %hv)
21 ; CHECK-DAG: lvx {{[0-9]+}}, 0, 3
22 ; CHECK-DAG: lvx {{[0-9]+}}, 3, [[REG]]
41 ; CHECK-DAG: lvx {{[0-9]+}}, 0, 3
42 ; CHECK-DAG: lvx {{[0-9]+}}, 3, [[REG]]
Dvec_shuffle_le.ll9 ; CHECK: lvx [[REG1:[0-9]+]]
10 ; CHECK: lvx [[REG2:[0-9]+]]
32 ; CHECK: lvx [[REG1:[0-9]+]]
33 ; CHECK: lvx [[REG2:[0-9]+]]
55 ; CHECK: lvx [[REG1:[0-9]+]]
56 ; CHECK: lvx [[REG2:[0-9]+]]
78 ; CHECK: lvx [[REG1:[0-9]+]]
79 ; CHECK: lvx [[REG2:[0-9]+]]
101 ; CHECK: lvx [[REG1:[0-9]+]]
102 ; CHECK: lvx [[REG2:[0-9]+]]
[all …]
Dbuiltins-ppc-p8vector.ll24 ; CHECK: lvx [[REG1:[0-9]+]], 0, 3
25 ; CHECK: lvx [[REG2:[0-9]+]], 0, 4
39 ; CHECK: lvx [[REG1:[0-9]+]], 0, 3
40 ; CHECK: lvx [[REG2:[0-9]+]], 0, 4
53 ; CHECK: lvx [[REG1:[0-9]+]],
66 ; CHECK: lvx [[REG1:[0-9]+]],
Dunal-vec-ldst.ll13 ; CHECK-DAG: lvx [[REG3:[0-9]+]], 3, [[REG1]]
14 ; CHECK-DAG: lvx [[REG4:[0-9]+]], 0, 3
28 ; CHECK-DAG: lvx [[REG4:[0-9]+]], 3, [[REG1]]
29 ; CHECK-DAG: lvx [[REG5:[0-9]+]], 3, [[REG2]]
30 ; CHECK-DAG: lvx [[REG6:[0-9]+]], 0, 3
44 ; CHECK-DAG: lvx [[REG3:[0-9]+]], 3, [[REG1]]
45 ; CHECK-DAG: lvx [[REG4:[0-9]+]], 0, 3
59 ; CHECK-DAG: lvx [[REG4:[0-9]+]], 3, [[REG1]]
60 ; CHECK-DAG: lvx [[REG5:[0-9]+]], 3, [[REG2]]
61 ; CHECK-DAG: lvx [[REG6:[0-9]+]], 0, 3
[all …]
Dunal-altivec.ll34 ; CHECK-DAG: lvx [[CNST:[0-9]+]],
40 ; CHECK-DAG: lvx [[LD1:[0-9]+]], [[B1]], [[C0]]
41 ; CHECK-DAG: lvx [[LD2:[0-9]+]], [[B3]], [[C15]]
42 ; CHECK-DAG: lvx [[LD3:[0-9]+]], [[B2]], [[C0]]
43 ; CHECK-DAG: lvx [[LD4:[0-9]+]], [[B4]], [[C15]]
Dunal-vec-negarith.ll12 ; CHECK-NOT: v4i32,ch = llvm.ppc.altivec.lvx{{.*}}<LD31[%p+4294967281](align=1)>
13 ; CHECK: v4i32,ch = llvm.ppc.altivec.lvx{{.*}}<LD31[%p+-15](align=1)>
Dmem-rr-addr-mode.ll4 ; Codegen lvx (R+16) as t = li 16, lvx t,R
/external/swiftshader/third_party/llvm-7.0/llvm/test/Transforms/InstCombine/PowerPC/
Daligned-altivec.ll5 declare <4 x i32> @llvm.ppc.altivec.lvx(i8*) #1
11 %vl = call <4 x i32> @llvm.ppc.altivec.lvx(i8* %hv)
14 ; CHECK: @llvm.ppc.altivec.lvx
26 %vl = call <4 x i32> @llvm.ppc.altivec.lvx(i8* %hv)
29 ; CHECK-NOT: @llvm.ppc.altivec.lvx
/external/llvm/test/Transforms/InstCombine/
Daligned-altivec.ll5 declare <4 x i32> @llvm.ppc.altivec.lvx(i8*) #1
11 %vl = call <4 x i32> @llvm.ppc.altivec.lvx(i8* %hv)
14 ; CHECK: @llvm.ppc.altivec.lvx
26 %vl = call <4 x i32> @llvm.ppc.altivec.lvx(i8* %hv)
29 ; CHECK-NOT: @llvm.ppc.altivec.lvx
/external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/PowerPC/
DREADME_ALTIVEC.txt8 The first should be a single lvx from the constant pool, the second should be
100 lvx v2, 0, r4
101 lvx v3, 0, r3
132 lvx v2, 0, r4
133 lvx v3, 0, r5
157 lvx v2, 0, r4
158 lvx v3, 0, r3
185 2. lvx the slot

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