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Searched refs:mask_tune_func (Results 1 – 4 of 4) sorted by relevance

/external/u-boot/drivers/ddr/marvell/a38x/
Dddr3_debug.c382 if (mask_tune_func & INIT_CONTROLLER_MASK_BIT) { in ddr3_tip_print_log()
389 if (mask_tune_func & SET_LOW_FREQ_MASK_BIT) { in ddr3_tip_print_log()
396 if (mask_tune_func & LOAD_PATTERN_MASK_BIT) { in ddr3_tip_print_log()
403 if (mask_tune_func & SET_MEDIUM_FREQ_MASK_BIT) { in ddr3_tip_print_log()
410 if (mask_tune_func & WRITE_LEVELING_MASK_BIT) { in ddr3_tip_print_log()
417 if (mask_tune_func & LOAD_PATTERN_2_MASK_BIT) { in ddr3_tip_print_log()
424 if (mask_tune_func & READ_LEVELING_MASK_BIT) { in ddr3_tip_print_log()
431 if (mask_tune_func & WRITE_LEVELING_SUPP_MASK_BIT) { in ddr3_tip_print_log()
438 if (mask_tune_func & PBS_RX_MASK_BIT) { in ddr3_tip_print_log()
445 if (mask_tune_func & PBS_TX_MASK_BIT) { in ddr3_tip_print_log()
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Dddr3_training.c82 u32 mask_tune_func = (SET_MEDIUM_FREQ_MASK_BIT | variable
2055 if (mask_tune_func & INIT_CONTROLLER_MASK_BIT) { in ddr3_tip_ddr3_training_main_flow()
2083 if (mask_tune_func & SET_LOW_FREQ_MASK_BIT) { in ddr3_tip_ddr3_training_main_flow()
2107 if (mask_tune_func & WRITE_LEVELING_LF_MASK_BIT) { in ddr3_tip_ddr3_training_main_flow()
2123 if (mask_tune_func & LOAD_PATTERN_MASK_BIT) { in ddr3_tip_ddr3_training_main_flow()
2151 if (mask_tune_func & SET_MEDIUM_FREQ_MASK_BIT) { in ddr3_tip_ddr3_training_main_flow()
2169 if (mask_tune_func & WRITE_LEVELING_MASK_BIT) { in ddr3_tip_ddr3_training_main_flow()
2191 if (mask_tune_func & LOAD_PATTERN_2_MASK_BIT) { in ddr3_tip_ddr3_training_main_flow()
2211 if (mask_tune_func & READ_LEVELING_MASK_BIT) { in ddr3_tip_ddr3_training_main_flow()
2232 if (mask_tune_func & WRITE_LEVELING_SUPP_MASK_BIT) { in ddr3_tip_ddr3_training_main_flow()
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Dmv_ddr_plat.c689 mask_tune_func = (SET_LOW_FREQ_MASK_BIT | in mv_ddr_training_mask_set()
705 mask_tune_func = (WRITE_LEVELING_MASK_BIT | in mv_ddr_training_mask_set()
718 mask_tune_func &= ~WRITE_LEVELING_SUPP_TF_MASK_BIT; in mv_ddr_training_mask_set()
719 mask_tune_func &= ~WRITE_LEVELING_SUPP_MASK_BIT; in mv_ddr_training_mask_set()
720 mask_tune_func &= ~PBS_TX_MASK_BIT; in mv_ddr_training_mask_set()
721 mask_tune_func &= ~PBS_RX_MASK_BIT; in mv_ddr_training_mask_set()
Dddr3_init.h83 extern u32 mask_tune_func;