1 /* SPDX-License-Identifier: GPL-2.0+ */ 2 /* 3 * Sun6i platform dram controller register and constant defines 4 * 5 * (C) Copyright 2007-2012 6 * Allwinner Technology Co., Ltd. <www.allwinnertech.com> 7 * Berg Xing <bergxing@allwinnertech.com> 8 * Tom Cubie <tangliang@allwinnertech.com> 9 * 10 * (C) Copyright 2014 Hans de Goede <hdegoede@redhat.com> 11 */ 12 13 #ifndef _SUNXI_DRAM_SUN6I_H 14 #define _SUNXI_DRAM_SUN6I_H 15 16 struct sunxi_mctl_com_reg { 17 u32 cr; /* 0x00 */ 18 u32 ccr; /* 0x04 controller configuration register */ 19 u32 dbgcr; /* 0x08 */ 20 u32 dbgcr1; /* 0x0c */ 21 u32 rmcr[8]; /* 0x10 */ 22 u32 mmcr[16]; /* 0x30 */ 23 u32 mbagcr[6]; /* 0x70 */ 24 u32 maer; /* 0x88 */ 25 u8 res0[0x14]; /* 0x8c */ 26 u32 mdfscr; /* 0x100 */ 27 u32 mdfsmer; /* 0x104 */ 28 u32 mdfsmrmr; /* 0x108 */ 29 u32 mdfstr0; /* 0x10c */ 30 u32 mdfstr1; /* 0x110 */ 31 u32 mdfstr2; /* 0x114 */ 32 u32 mdfstr3; /* 0x118 */ 33 u32 mdfsgcr; /* 0x11c */ 34 u8 res1[0x1c]; /* 0x120 */ 35 u32 mdfsivr; /* 0x13c */ 36 u8 res2[0x0c]; /* 0x140 */ 37 u32 mdfstcr; /* 0x14c */ 38 }; 39 40 struct sunxi_mctl_ctl_reg { 41 u8 res0[0x04]; /* 0x00 */ 42 u32 sctl; /* 0x04 */ 43 u32 sstat; /* 0x08 */ 44 u8 res1[0x34]; /* 0x0c */ 45 u32 mcmd; /* 0x40 */ 46 u8 res2[0x08]; /* 0x44 */ 47 u32 cmdstat; /* 0x4c */ 48 u32 cmdstaten; /* 0x50 */ 49 u8 res3[0x0c]; /* 0x54 */ 50 u32 mrrcfg0; /* 0x60 */ 51 u32 mrrstat0; /* 0x64 */ 52 u32 mrrstat1; /* 0x68 */ 53 u8 res4[0x10]; /* 0x6c */ 54 u32 mcfg1; /* 0x7c */ 55 u32 mcfg; /* 0x80 */ 56 u32 ppcfg; /* 0x84 */ 57 u32 mstat; /* 0x88 */ 58 u32 lp2zqcfg; /* 0x8c */ 59 u8 res5[0x04]; /* 0x90 */ 60 u32 dtustat; /* 0x94 */ 61 u32 dtuna; /* 0x98 */ 62 u32 dtune; /* 0x9c */ 63 u32 dtuprd0; /* 0xa0 */ 64 u32 dtuprd1; /* 0xa4 */ 65 u32 dtuprd2; /* 0xa8 */ 66 u32 dtuprd3; /* 0xac */ 67 u32 dtuawdt; /* 0xb0 */ 68 u8 res6[0x0c]; /* 0xb4 */ 69 u32 togcnt1u; /* 0xc0 */ 70 u8 res7[0x08]; /* 0xc4 */ 71 u32 togcnt100n; /* 0xcc */ 72 u32 trefi; /* 0xd0 */ 73 u32 tmrd; /* 0xd4 */ 74 u32 trfc; /* 0xd8 */ 75 u32 trp; /* 0xdc */ 76 u32 trtw; /* 0xe0 */ 77 u32 tal; /* 0xe4 */ 78 u32 tcl; /* 0xe8 */ 79 u32 tcwl; /* 0xec */ 80 u32 tras; /* 0xf0 */ 81 u32 trc; /* 0xf4 */ 82 u32 trcd; /* 0xf8 */ 83 u32 trrd; /* 0xfc */ 84 u32 trtp; /* 0x100 */ 85 u32 twr; /* 0x104 */ 86 u32 twtr; /* 0x108 */ 87 u32 texsr; /* 0x10c */ 88 u32 txp; /* 0x110 */ 89 u32 txpdll; /* 0x114 */ 90 u32 tzqcs; /* 0x118 */ 91 u32 tzqcsi; /* 0x11c */ 92 u32 tdqs; /* 0x120 */ 93 u32 tcksre; /* 0x124 */ 94 u32 tcksrx; /* 0x128 */ 95 u32 tcke; /* 0x12c */ 96 u32 tmod; /* 0x130 */ 97 u32 trstl; /* 0x134 */ 98 u32 tzqcl; /* 0x138 */ 99 u32 tmrr; /* 0x13c */ 100 u32 tckesr; /* 0x140 */ 101 u32 tdpd; /* 0x144 */ 102 u8 res8[0xb8]; /* 0x148 */ 103 u32 dtuwactl; /* 0x200 */ 104 u32 dturactl; /* 0x204 */ 105 u32 dtucfg; /* 0x208 */ 106 u32 dtuectl; /* 0x20c */ 107 u32 dtuwd0; /* 0x210 */ 108 u32 dtuwd1; /* 0x214 */ 109 u32 dtuwd2; /* 0x218 */ 110 u32 dtuwd3; /* 0x21c */ 111 u32 dtuwdm; /* 0x220 */ 112 u32 dturd0; /* 0x224 */ 113 u32 dturd1; /* 0x228 */ 114 u32 dturd2; /* 0x22c */ 115 u32 dturd3; /* 0x230 */ 116 u32 dtulfsrwd; /* 0x234 */ 117 u32 dtulfsrrd; /* 0x238 */ 118 u32 dtueaf; /* 0x23c */ 119 u32 dfitctldly; /* 0x240 */ 120 u32 dfiodtcfg; /* 0x244 */ 121 u32 dfiodtcfg1; /* 0x248 */ 122 u32 dfiodtrmap; /* 0x24c */ 123 u32 dfitphywrd; /* 0x250 */ 124 u32 dfitphywrl; /* 0x254 */ 125 u8 res9[0x08]; /* 0x258 */ 126 u32 dfitrdden; /* 0x260 */ 127 u32 dfitphyrdl; /* 0x264 */ 128 u8 res10[0x08]; /* 0x268 */ 129 u32 dfitphyupdtype0; /* 0x270 */ 130 u32 dfitphyupdtype1; /* 0x274 */ 131 u32 dfitphyupdtype2; /* 0x278 */ 132 u32 dfitphyupdtype3; /* 0x27c */ 133 u32 dfitctrlupdmin; /* 0x280 */ 134 u32 dfitctrlupdmax; /* 0x284 */ 135 u32 dfitctrlupddly; /* 0x288 */ 136 u8 res11[4]; /* 0x28c */ 137 u32 dfiupdcfg; /* 0x290 */ 138 u32 dfitrefmski; /* 0x294 */ 139 u32 dfitcrlupdi; /* 0x298 */ 140 u8 res12[0x10]; /* 0x29c */ 141 u32 dfitrcfg0; /* 0x2ac */ 142 u32 dfitrstat0; /* 0x2b0 */ 143 u32 dfitrwrlvlen; /* 0x2b4 */ 144 u32 dfitrrdlvlen; /* 0x2b8 */ 145 u32 dfitrrdlvlgateen; /* 0x2bc */ 146 u8 res13[0x04]; /* 0x2c0 */ 147 u32 dfistcfg0; /* 0x2c4 */ 148 u32 dfistcfg1; /* 0x2c8 */ 149 u8 res14[0x04]; /* 0x2cc */ 150 u32 dfitdramclken; /* 0x2d0 */ 151 u32 dfitdramclkdis; /* 0x2d4 */ 152 u8 res15[0x18]; /* 0x2d8 */ 153 u32 dfilpcfg0; /* 0x2f0 */ 154 }; 155 156 struct sunxi_mctl_phy_reg { 157 u8 res0[0x04]; /* 0x00 */ 158 u32 pir; /* 0x04 */ 159 u32 pgcr; /* 0x08 phy general configuration register */ 160 u32 pgsr; /* 0x0c */ 161 u32 dllgcr; /* 0x10 */ 162 u32 acdllcr; /* 0x14 */ 163 u32 ptr0; /* 0x18 */ 164 u32 ptr1; /* 0x1c */ 165 u32 ptr2; /* 0x20 */ 166 u32 aciocr; /* 0x24 */ 167 u32 dxccr; /* 0x28 DATX8 common configuration register */ 168 u32 dsgcr; /* 0x2c dram system general config register */ 169 u32 dcr; /* 0x30 */ 170 u32 dtpr0; /* 0x34 dram timing parameters register 0 */ 171 u32 dtpr1; /* 0x38 dram timing parameters register 1 */ 172 u32 dtpr2; /* 0x3c dram timing parameters register 2 */ 173 u32 mr0; /* 0x40 mode register 0 */ 174 u32 mr1; /* 0x44 mode register 1 */ 175 u32 mr2; /* 0x48 mode register 2 */ 176 u32 mr3; /* 0x4c mode register 3 */ 177 u32 odtcr; /* 0x50 */ 178 u32 dtar; /* 0x54 data training address register */ 179 u32 dtd0; /* 0x58 */ 180 u32 dtd1; /* 0x5c */ 181 u8 res1[0x60]; /* 0x60 */ 182 u32 dcuar; /* 0xc0 */ 183 u32 dcudr; /* 0xc4 */ 184 u32 dcurr; /* 0xc8 */ 185 u32 dculr; /* 0xcc */ 186 u32 dcugcr; /* 0xd0 */ 187 u32 dcutpr; /* 0xd4 */ 188 u32 dcusr0; /* 0xd8 */ 189 u32 dcusr1; /* 0xdc */ 190 u8 res2[0x20]; /* 0xe0 */ 191 u32 bistrr; /* 0x100 */ 192 u32 bistmskr0; /* 0x104 */ 193 u32 bistmskr1; /* 0x108 */ 194 u32 bistwcr; /* 0x10c */ 195 u32 bistlsr; /* 0x110 */ 196 u32 bistar0; /* 0x114 */ 197 u32 bistar1; /* 0x118 */ 198 u32 bistar2; /* 0x11c */ 199 u32 bistupdr; /* 0x120 */ 200 u32 bistgsr; /* 0x124 */ 201 u32 bistwer; /* 0x128 */ 202 u32 bistber0; /* 0x12c */ 203 u32 bistber1; /* 0x130 */ 204 u32 bistber2; /* 0x134 */ 205 u32 bistwcsr; /* 0x138 */ 206 u32 bistfwr0; /* 0x13c */ 207 u32 bistfwr1; /* 0x140 */ 208 u8 res3[0x3c]; /* 0x144 */ 209 u32 zq0cr0; /* 0x180 zq 0 control register 0 */ 210 u32 zq0cr1; /* 0x184 zq 0 control register 1 */ 211 u32 zq0sr0; /* 0x188 zq 0 status register 0 */ 212 u32 zq0sr1; /* 0x18c zq 0 status register 1 */ 213 u8 res4[0x30]; /* 0x190 */ 214 u32 dx0gcr; /* 0x1c0 */ 215 u32 dx0gsr0; /* 0x1c4 */ 216 u32 dx0gsr1; /* 0x1c8 */ 217 u32 dx0dllcr; /* 0x1cc */ 218 u32 dx0dqtr; /* 0x1d0 */ 219 u32 dx0dqstr; /* 0x1d4 */ 220 u8 res5[0x28]; /* 0x1d8 */ 221 u32 dx1gcr; /* 0x200 */ 222 u32 dx1gsr0; /* 0x204 */ 223 u32 dx1gsr1; /* 0x208 */ 224 u32 dx1dllcr; /* 0x20c */ 225 u32 dx1dqtr; /* 0x210 */ 226 u32 dx1dqstr; /* 0x214 */ 227 u8 res6[0x28]; /* 0x218 */ 228 u32 dx2gcr; /* 0x240 */ 229 u32 dx2gsr0; /* 0x244 */ 230 u32 dx2gsr1; /* 0x248 */ 231 u32 dx2dllcr; /* 0x24c */ 232 u32 dx2dqtr; /* 0x250 */ 233 u32 dx2dqstr; /* 0x254 */ 234 u8 res7[0x28]; /* 0x258 */ 235 u32 dx3gcr; /* 0x280 */ 236 u32 dx3gsr0; /* 0x284 */ 237 u32 dx3gsr1; /* 0x288 */ 238 u32 dx3dllcr; /* 0x28c */ 239 u32 dx3dqtr; /* 0x290 */ 240 u32 dx3dqstr; /* 0x294 */ 241 }; 242 243 /* 244 * DRAM common (sunxi_mctl_com_reg) register constants. 245 */ 246 #define MCTL_CR_RANK_MASK (3 << 0) 247 #define MCTL_CR_RANK(x) (((x) - 1) << 0) 248 #define MCTL_CR_BANK_MASK (3 << 2) 249 #define MCTL_CR_BANK(x) ((x) << 2) 250 #define MCTL_CR_ROW_MASK (0xf << 4) 251 #define MCTL_CR_ROW(x) (((x) - 1) << 4) 252 #define MCTL_CR_PAGE_SIZE_MASK (0xf << 8) 253 #define MCTL_CR_PAGE_SIZE(x) ((fls(x) - 4) << 8) 254 #define MCTL_CR_BUSW_MASK (3 << 12) 255 #define MCTL_CR_BUSW16 (1 << 12) 256 #define MCTL_CR_BUSW32 (3 << 12) 257 #define MCTL_CR_SEQUENCE (1 << 15) 258 #define MCTL_CR_DDR3 (3 << 16) 259 #define MCTL_CR_CHANNEL_MASK (1 << 19) 260 #define MCTL_CR_CHANNEL(x) (((x) - 1) << 19) 261 #define MCTL_CR_UNKNOWN ((1 << 22) | (1 << 20)) 262 #define MCTL_CCR_CH0_CLK_EN (1 << 0) 263 #define MCTL_CCR_CH1_CLK_EN (1 << 1) 264 #define MCTL_CCR_MASTER_CLK_EN (1 << 2) 265 266 /* 267 * DRAM control (sunxi_mctl_ctl_reg) register constants. 268 * Note that we use constant values for a lot of the timings, this is what 269 * the original boot0 bootloader does. 270 */ 271 #define MCTL_SCTL_CONFIG 1 272 #define MCTL_SCTL_ACCESS 2 273 #define MCTL_MCMD_NOP 0x88000000 274 #define MCTL_MCMD_BUSY 0x80000000 275 #define MCTL_MCFG_DDR3 0x70061 276 #define MCTL_TREFI 78 277 #define MCTL_TMRD 4 278 #define MCTL_TRFC 115 279 #define MCTL_TRP 9 280 #define MCTL_TPREA 0 281 #define MCTL_TRTW 2 282 #define MCTL_TAL 0 283 #define MCTL_TCL 9 284 #define MCTL_TCWL 8 285 #define MCTL_TRAS 18 286 #define MCTL_TRC 23 287 #define MCTL_TRCD 9 288 #define MCTL_TRRD 4 289 #define MCTL_TRTP 4 290 #define MCTL_TWR 8 291 #define MCTL_TWTR 4 292 #define MCTL_TEXSR 512 293 #define MCTL_TXP 4 294 #define MCTL_TXPDLL 14 295 #define MCTL_TZQCS 64 296 #define MCTL_TZQCSI 0 297 #define MCTL_TDQS 1 298 #define MCTL_TCKSRE 5 299 #define MCTL_TCKSRX 5 300 #define MCTL_TCKE 4 301 #define MCTL_TMOD 12 302 #define MCTL_TRSTL 80 303 #define MCTL_TZQCL 512 304 #define MCTL_TMRR 2 305 #define MCTL_TCKESR 5 306 #define MCTL_TDPD 0 307 #define MCTL_DFITPHYRDL 15 308 #define MCTL_DFIUPDCFG_UPD (1 << 1) 309 #define MCTL_DFISTCFG0 5 310 311 /* 312 * DRAM phy (sunxi_mctl_phy_reg) register values / constants. 313 */ 314 #define MCTL_PIR_CLEAR_STATUS (1 << 28) 315 #define MCTL_PIR_STEP1 0xe9 316 #define MCTL_PIR_STEP2 0x81 317 #define MCTL_PGCR_RANK (1 << 19) 318 #define MCTL_PGCR 0x018c0202 319 #define MCTL_PGSR_TRAIN_ERR_MASK (3 << 5) 320 /* constants for both acdllcr as well as dx#dllcr */ 321 #define MCTL_DLLCR_NRESET (1 << 30) 322 #define MCTL_DLLCR_DISABLE (1 << 31) 323 /* ptr constants these are or-ed together to get the final ptr# values */ 324 #define MCTL_TITMSRST 10 325 #define MCTL_TDLLLOCK 2250 326 #define MCTL_TDLLSRST 23 327 #define MCTL_TDINIT0 217000 328 #define MCTL_TDINIT1 160 329 #define MCTL_TDINIT2 87000 330 #define MCTL_TDINIT3 433 331 /* end ptr constants */ 332 #define MCTL_ACIOCR_DISABLE ((3 << 18) | (1 << 8) | (1 << 3)) 333 #define MCTL_DXCCR_DISABLE ((1 << 3) | (1 << 2)) 334 #define MCTL_DXCCR 0x800 335 #define MCTL_DSGCR_ENABLE (1 << 28) 336 #define MCTL_DSGCR 0xf200001b 337 #define MCTL_DCR_DDR3 0x0b 338 /* dtpr constants these are or-ed together to get the final dtpr# values */ 339 #define MCTL_TCCD 0 340 #define MCTL_TDQSCKMAX 1 341 #define MCTL_TDQSCK 1 342 #define MCTL_TRTODT 0 343 #define MCTL_TFAW 20 344 #define MCTL_TAOND 0 345 #define MCTL_TDLLK 512 346 /* end dtpr constants */ 347 #define MCTL_MR0 0x1a50 348 #define MCTL_MR1 0x4 349 #define MCTL_MR2 ((MCTL_TCWL - 5) << 3) 350 #define MCTL_MR3 0x0 351 #define MCTL_DX_GCR_EN (1 << 0) 352 #define MCTL_DX_GCR 0x880 353 #define MCTL_DX_GSR0_RANK0_TRAIN_DONE (1 << 0) 354 #define MCTL_DX_GSR0_RANK1_TRAIN_DONE (1 << 1) 355 #define MCTL_DX_GSR0_RANK0_TRAIN_ERR (1 << 4) 356 #define MCTL_DX_GSR0_RANK1_TRAIN_ERR (1 << 5) 357 358 #endif /* _SUNXI_DRAM_SUN6I_H */ 359