| /external/arm-trusted-firmware/plat/rockchip/rk3399/drivers/dram/ |
| D | dfs.c | 28 {.mhz = 928, .refdiv = 1, .fbdiv = 116, .postdiv1 = 3, .postdiv2 = 1},
29 {.mhz = 800, .refdiv = 1, .fbdiv = 100, .postdiv1 = 3, .postdiv2 = 1},
30 {.mhz = 732, .refdiv = 1, .fbdiv = 61, .postdiv1 = 2, .postdiv2 = 1},
31 {.mhz = 666, .refdiv = 1, .fbdiv = 111, .postdiv1 = 4, .postdiv2 = 1},
32 {.mhz = 600, .refdiv = 1, .fbdiv = 50, .postdiv1 = 2, .postdiv2 = 1},
33 {.mhz = 528, .refdiv = 1, .fbdiv = 66, .postdiv1 = 3, .postdiv2 = 1},
34 {.mhz = 400, .refdiv = 1, .fbdiv = 50, .postdiv1 = 3, .postdiv2 = 1},
35 {.mhz = 300, .refdiv = 1, .fbdiv = 50, .postdiv1 = 4, .postdiv2 = 1},
36 {.mhz = 200, .refdiv = 1, .fbdiv = 50, .postdiv1 = 3, .postdiv2 = 2},
328 delay_adder = ie_enable / (1000000 / pdram_timing->mhz); in get_pi_rdlat_adj()
[all …]
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| D | dram_spec_timing.c | 212 pdram_timing->mhz = nmhz; in ddr3_get_parameter()
428 pdram_timing->mhz = nmhz; in lpddr2_get_parameter()
668 pdram_timing->mhz = nmhz; in lpddr3_get_parameter()
964 pdram_timing->mhz = nmhz; in lpddr4_get_parameter()
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| D | dram_spec_timing.h | 63 uint32_t mhz; member
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| /external/u-boot/arch/xtensa/lib/ |
| D | time.c | 53 ulong mhz = CONFIG_SYS_CLK_FREQ / 1000000; in __udelay() local
60 delay_cycles(mhz << 22); in __udelay()
61 delay_cycles(mhz * lo); in __udelay()
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| /external/u-boot/arch/xtensa/cpu/ |
| D | cpu.c | 31 char buf[120], mhz[8]; in print_cpuinfo() local
39 XCHAL_CORE_ID, id0, id1, strmhz(mhz, gd->cpu_clk)); in print_cpuinfo()
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| /external/mesa3d/src/util/ |
| D | timespec.h | 294 millihz_to_nsec(uint32_t mhz) in millihz_to_nsec() argument
296 assert(mhz > 0); in millihz_to_nsec()
297 return 1000000000000LL / mhz; in millihz_to_nsec()
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| /external/u-boot/drivers/ram/rockchip/ |
| D | sdram_rk3328.c | 78 u32 mhz = hz / MHZ; in rkclk_set_dpll() local
81 if (mhz <= 300) { in rkclk_set_dpll()
84 } else if (mhz <= 400) { in rkclk_set_dpll()
87 } else if (mhz <= 600) { in rkclk_set_dpll()
90 } else if (mhz <= 800) { in rkclk_set_dpll()
93 } else if (mhz <= 1600) { in rkclk_set_dpll()
100 fbdiv = (mhz * refdiv * postdiv1 * postdiv2) / 24; in rkclk_set_dpll()
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| D | sdram_px30.c | 147 u32 mhz = hz / MHz; in rkclk_set_dpll() local
150 if (mhz <= 300) { in rkclk_set_dpll()
153 } else if (mhz <= 400) { in rkclk_set_dpll()
156 } else if (mhz <= 600) { in rkclk_set_dpll()
159 } else if (mhz <= 800) { in rkclk_set_dpll()
162 } else if (mhz <= 1600) { in rkclk_set_dpll()
169 fbdiv = (mhz * refdiv * postdiv1 * postdiv2) / 24; in rkclk_set_dpll()
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| /external/u-boot/arch/arm/dts/ |
| D | imx6sx-softing-vining-2000.dts | 436 pinctrl_usdhc2_50mhz: usdhc2grp-50mhz {
449 pinctrl_usdhc2_100mhz: usdhc2grp-100mhz {
460 pinctrl_usdhc2_200mhz: usdhc2grp-200mhz {
471 pinctrl_usdhc4_50mhz: usdhc4grp-50mhz {
487 pinctrl_usdhc4_100mhz: usdhc4-100mhz {
502 pinctrl_usdhc4_200mhz: usdhc4-200mhz {
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| D | vexpress-v2p-ca15_a7.dts | 44 capacity-dmips-mhz = <1024>;
54 capacity-dmips-mhz = <1024>;
64 capacity-dmips-mhz = <516>;
74 capacity-dmips-mhz = <516>;
84 capacity-dmips-mhz = <516>;
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| D | imx6sx-sabreauto.dts | 179 pinctrl_usdhc3_100mhz: usdhc3grp-100mhz {
194 pinctrl_usdhc3_200mhz: usdhc3grp-200mhz {
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| D | hi3660.dtsi | 65 capacity-dmips-mhz = <592>;
79 capacity-dmips-mhz = <592>;
92 capacity-dmips-mhz = <592>;
105 capacity-dmips-mhz = <592>;
118 capacity-dmips-mhz = <1024>;
132 capacity-dmips-mhz = <1024>;
145 capacity-dmips-mhz = <1024>;
158 capacity-dmips-mhz = <1024>;
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| D | imx6-logicpd-baseboard.dtsi | 533 pinctrl_usdhc2_100mhz: h100-usdhc2-100mhz {
545 pinctrl_usdhc2_200mhz: h100-usdhc2-200mhz {
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| D | r8a7790.dtsi | 82 capacity-dmips-mhz = <1024>;
103 capacity-dmips-mhz = <1024>;
124 capacity-dmips-mhz = <1024>;
145 capacity-dmips-mhz = <1024>;
166 capacity-dmips-mhz = <539>;
177 capacity-dmips-mhz = <539>;
188 capacity-dmips-mhz = <539>;
199 capacity-dmips-mhz = <539>;
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| D | imx6sx-sdb.dtsi | 563 pinctrl_usdhc3_100mhz: usdhc3grp-100mhz {
578 pinctrl_usdhc3_200mhz: usdhc3grp-200mhz {
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| D | imx6ull-colibri.dtsi | 539 pinctrl_usdhc1_100mhz: usdhc1-100mhz-grp {
550 pinctrl_usdhc1_200mhz: usdhc1-200mhz-grp {
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| D | r8a7795.dtsi | 160 capacity-dmips-mhz = <1024>;
173 capacity-dmips-mhz = <1024>;
186 capacity-dmips-mhz = <1024>;
199 capacity-dmips-mhz = <1024>;
212 capacity-dmips-mhz = <535>;
224 capacity-dmips-mhz = <535>;
236 capacity-dmips-mhz = <535>;
248 capacity-dmips-mhz = <535>;
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| D | r8a7796.dtsi | 165 capacity-dmips-mhz = <1024>;
178 capacity-dmips-mhz = <1024>;
191 capacity-dmips-mhz = <535>;
203 capacity-dmips-mhz = <535>;
215 capacity-dmips-mhz = <535>;
227 capacity-dmips-mhz = <535>;
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| /external/u-boot/arch/arc/lib/ |
| D | cpu.c | 219 char mhz[8]; in print_cpuinfo() local
222 strmhz(mhz, gd->cpu_clk)); in print_cpuinfo()
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| /external/u-boot/board/hisilicon/hikey/ |
| D | README | 125 INFO: succeed to set ddrc 150mhz
127 INFO: succeed to set ddrc 266mhz
129 INFO: succeed to set ddrc 400mhz
131 INFO: succeed to set ddrc 533mhz
133 INFO: succeed to set ddrc 800mhz
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| /external/autotest/server/ |
| D | site_linux_system.py | 179 for mhz in band.frequencies:
180 if mhz not in phys_for_frequency:
181 phys_for_frequency[mhz] = [phy.name]
183 phys_for_frequency[mhz].append(phy.name)
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| /external/u-boot/arch/arm/mach-tegra/tegra124/ |
| D | clock.c | 1070 mhz = 1000 * 1000, min_vco = 500 * mhz, max_vco = 1000 * mhz, in clock_set_display_rate() local
1071 min_cf = 1 * mhz, max_cf = 6 * mhz; in clock_set_display_rate()
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| /external/u-boot/doc/device-tree-bindings/clock/ |
| D | rockchip,rk3188-cru.txt | 34 - "xin27m" - 27mhz crystal input on rk3066 - optional,
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| /external/arm-trusted-firmware/plat/rockchip/rk3399/drivers/soc/ |
| D | soc.h | 124 uint32_t mhz; member
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| /external/u-boot/doc/device-tree-bindings/phy/ |
| D | phy-mtk-tphy.txt | 23 - mediatek,src-ref-clk-mhz : frequency of reference clock for slew rate
|