| /external/swiftshader/third_party/llvm-7.0/llvm/test/CodeGen/RISCV/ |
| D | mul.ll | 91 ; RV32IM-NEXT: mulhu a4, a0, a2
117 ; RV32IM-NEXT: mulhu a3, a0, a2
151 define i32 @mulhu(i32 %a, i32 %b) nounwind {
152 ; RV32I-LABEL: mulhu:
165 ; RV32IM-LABEL: mulhu:
167 ; RV32IM-NEXT: mulhu a0, a0, a1
|
| D | div.ll | 40 ; RV32IM-NEXT: mulhu a0, a0, a1
|
| /external/llvm/test/CodeGen/PowerPC/ |
| D | vec_urem_const.ll | 6 ; Common code used to replace the urem by a mulhu, and compilation would
7 ; then crash since mulhu isn't supported on vector types.
|
| /external/swiftshader/third_party/llvm-7.0/llvm/test/CodeGen/PowerPC/ |
| D | vec_urem_const.ll | 6 ; Common code used to replace the urem by a mulhu, and compilation would
7 ; then crash since mulhu isn't supported on vector types.
|
| /external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/RISCV/ |
| D | RISCVInstrInfoM.td | 23 def MULHU : ALU_rr<0b0000001, 0b011, "mulhu">;
45 def : PatGprGpr<mulhu, MULHU>;
|
| /external/swiftshader/third_party/llvm-7.0/llvm/test/MC/RISCV/ |
| D | rv32m-valid.s | 21 # CHECK-INST: mulhu a5, a4, a3
23 mulhu a5, a4, a3 label
|
| /external/elfutils/tests/ |
| D | testfile-riscv64-dis1.expect.bz2 | |
| /external/llvm/lib/Target/Mips/ |
| D | Mips64r6InstrInfo.td | 70 class DMUHU_DESC : MUL_R6_DESC_BASE<"dmuhu", GPR64Opnd, II_DMUHU, mulhu>;
|
| D | MicroMips64r6InstrInfo.td | 208 mulhu>;
|
| D | Mips32r6InstrInfo.td | 539 class MUHU_DESC : MUL_R6_DESC_BASE<"muhu", GPR32Opnd, II_MUHU, mulhu>;
|
| D | MicroMips32r6InstrInfo.td | 342 class MUHU_MMR6_DESC : ArithLogicR<"muhu", GPR32Opnd, 1, II_MUHU, mulhu>;
|
| /external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/Mips/ |
| D | Mips64r6InstrInfo.td | 72 class DMUHU_DESC : MUL_R6_DESC_BASE<"dmuhu", GPR64Opnd, II_DMUHU, mulhu>;
|
| D | Mips32r6InstrInfo.td | 593 class MUHU_DESC : MUL_R6_DESC_BASE<"muhu", GPR32Opnd, II_MUHU, mulhu>;
|
| D | MicroMips32r6InstrInfo.td | 348 class MUHU_MMR6_DESC : ArithLogicR<"muhu", GPR32Opnd, 1, II_MUHU, mulhu>;
|
| /external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/Hexagon/ |
| D | HexagonPatterns.td | 1243 def: OpR_RR_pat<M2_mpyu_up, pf2<mulhu>, i32, I32>;
1283 def: Pat<(v2i32 (mulhu V2I32:$Rss, V2I32:$Rtt)),
1300 def: Pat<(v8i8 (mulhu V8I8:$Rss, V8I8:$Rtt)),
1325 def: Pat<(v4i16 (mulhu V4I16:$Rss, V4I16:$Rtt)),
1456 def : Pat <(mulhu I64:$Rss, I64:$Rtt), (MulHU $Rss, $Rtt)>;
|
| /external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/AMDGPU/ |
| D | VOP3Instructions.td | 303 def V_MUL_HI_U32 : VOP3Inst <"v_mul_hi_u32", VOP3_Profile<VOP_I32_I32_I32>, mulhu>;
|
| D | R600Instructions.td | 1116 inst, "MULHI", mulhu> {
|
| /external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/ARC/ |
| D | ARCInstrInfo.td | 256 defm : MultiPat<mulhu, MPYMU_rrr, MPYMU_rru6, MPYMU_rrlimm>;
|
| /external/llvm/lib/Target/AMDGPU/ |
| D | R600Instructions.td | 1081 inst, "MULHI", mulhu
|
| /external/llvm/include/llvm/Target/ |
| D | TargetSelectionDAG.td | 371 def mulhu : SDNode<"ISD::MULHU" , SDTIntBinOp, [SDNPCommutative]>;
|
| /external/swiftshader/third_party/llvm-7.0/llvm/include/llvm/Target/ |
| D | TargetSelectionDAG.td | 349 def mulhu : SDNode<"ISD::MULHU" , SDTIntBinOp, [SDNPCommutative]>;
|
| /external/llvm/lib/Target/PowerPC/ |
| D | PPCInstr64Bit.td | 564 [(set i64:$rT, (mulhu i64:$rA, i64:$rB))]>;
|
| /external/llvm/lib/Target/NVPTX/ |
| D | NVPTXVector.td | 436 defm VMultHU : IntBinVOp<"mul.hi.u", mulhu, MULTHUi64rr, MULTHUi32rr,
|
| /external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/PowerPC/ |
| D | PPCInstr64Bit.td | 640 [(set i64:$rT, (mulhu i64:$rA, i64:$rB))]>;
|
| /external/llvm/lib/Target/Hexagon/ |
| D | HexagonInstrInfo.td | 2696 def: Pat<(i32 (mulhu I32:$src1, I32:$src2)), (M2_mpyu_up I32:$src1, I32:$src2)>;
5051 def : Pat <(mulhu (i64 DoubleRegs:$src1), (i64 DoubleRegs:$src2)),
|