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Searched refs:nir_op_f2u64 (Results 1 – 19 of 19) sorted by relevance

/external/mesa3d/prebuilt-intermediates/bifrost/
Dbifrost_nir_algebraic.c1938 nir_op_f2u64,
2036 nir_op_f2u64,
2048 nir_op_f2u64,
2058 nir_op_f2u64,
2069 nir_op_f2u64,
/external/mesa3d/prebuilt-intermediates/nir/
Dnir_opcodes.h160 nir_op_f2u64, enumerator
Dnir_opcodes.c181 return nir_op_f2u64; in nir_type_conversion_op()
Dnir_builder_opcodes.h671 return nir_build_alu(build, nir_op_f2u64, src0, NULL, NULL, NULL); in nir_f2u64()
Dnir_opt_algebraic.c16617 nir_op_f2u64,
16627 nir_op_f2u64,
17570 nir_op_f2u64,
17580 nir_op_f2u64,
18262 nir_op_f2u64,
18275 nir_op_f2u64,
Dnir_constant_expressions.c46849 case nir_op_f2u64: in nir_eval_const_opcode()
/external/mesa3d/prebuilt-intermediates/midgard/
Dmidgard_nir_algebraic.c1541 nir_op_f2u64,
1590 nir_op_f2u64,
1602 nir_op_f2u64,
/external/mesa3d/src/compiler/nir/
Dnir_lower_int64.c831 case nir_op_f2u64: in nir_lower_int64_op_to_options_mask()
986 case nir_op_f2u64: in lower_int64_alu_instr()
1064 case nir_op_f2u64: in should_lower_int64_alu_instr()
Dnir_lower_double_ops.c479 case nir_op_f2u64: in lower_doubles_instr_to_soft()
/external/mesa3d/src/gallium/drivers/nouveau/codegen/
Dnv50_ir_from_nir.cpp402 case nir_op_f2u64: in getOperation()
2558 case nir_op_f2u64: in visit()
2566 if (op == nir_op_f2i32 || op == nir_op_f2i64 || op == nir_op_f2u32 || op == nir_op_f2u64) in visit()
/external/mesa3d/src/amd/compiler/
Daco_instruction_selection_setup.cpp730 case nir_op_f2u64: in init_context()
Daco_instruction_selection.cpp2456 case nir_op_f2u64: { in visit_alu_instr()
/external/mesa3d/src/panfrost/bifrost/
Dbifrost_compile.c969 case nir_op_f2u64: in bi_class_for_nir_alu()
/external/mesa3d/src/gallium/auxiliary/nir/
Dnir_to_tgsi.c591 [nir_op_f2u64] = { TGSI_OPCODE_F2U64, TGSI_OPCODE_D2U64 }, in ntt_emit_alu()
/external/mesa3d/src/gallium/auxiliary/gallivm/
Dlp_bld_nir.c595 case nir_op_f2u64: in do_alu_action()
/external/mesa3d/src/intel/compiler/
Dbrw_fs_nir.cpp1112 case nir_op_f2u64: in nir_emit_alu()
/external/mesa3d/src/amd/llvm/
Dac_nir_to_llvm.c899 case nir_op_f2u64: in visit_alu()
/external/mesa3d/docs/relnotes/
D20.0.0.rst3210 - aco: implement nir_op_f2i64/nir_op_f2u64 on GFX6
D20.1.0.rst3984 - aco: implement 16-bit nir_op_f2i64/nir_op_f2u64