| /external/mesa3d/src/freedreno/ir3/ |
| D | ir3_nir_lower_tg4_to_tex.c | 92 nir_instr_as_tex(instr)->op == nir_texop_tg4); in ir3_nir_lower_tg4_to_tex_filter()
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| D | ir3_compiler_nir.c | 2264 case nir_texop_tg4: in emit_tex()
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| /external/mesa3d/src/broadcom/compiler/ |
| D | v3d40_tex.c | 75 .gather_mode = instr->op == nir_texop_tg4, in v3d40_vir_emit_tex()
80 .disable_autolod = instr->op == nir_texop_tg4 in v3d40_vir_emit_tex()
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| D | v3d33_tex.c | 97 instr->op != nir_texop_tg4) { in v3d33_vir_emit_tex()
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| /external/mesa3d/src/compiler/nir/ |
| D | nir_lower_tex.c | 768 if (tex->op == nir_texop_tg4) { in swizzle_result()
922 assert(tex->op == nir_texop_tg4); in lower_tg4_offsets()
1091 if (tex->op == nir_texop_tg4 && options->lower_tg4_broadcom_swizzle) { in nir_lower_tex_block()
1176 if (tex->op == nir_texop_tg4 && in nir_lower_tex_block()
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| D | nir_print.c | 1127 case nir_texop_tg4: in print_tex_instr()
1226 if (instr->op == nir_texop_tg4) { in print_tex_instr()
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| D | nir_gather_info.c | 700 case nir_texop_tg4: in gather_tex_info()
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| D | nir_serialize.c | 1483 if (tex->op == nir_texop_tg4) in write_tex()
1518 if (tex->op == nir_texop_tg4) in read_tex()
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| D | nir.h | 2222 nir_texop_tg4, /**< Texture gather */ enumerator
2377 case nir_texop_tg4: in nir_tex_instr_is_query()
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| D | nir_validate.c | 822 validate_assert(state, instr->op == nir_texop_tg4); in validate_tex_instr()
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| D | nir.c | 684 if (tex->op != nir_texop_tg4) in nir_tex_instr_has_explicit_tg4_offsets()
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| /external/mesa3d/src/gallium/drivers/r600/sfn/ |
| D | sfn_instruction_tex.cpp | 178 if (tex->op == nir_texop_tg4 && in r600_nir_lower_int_tg4_impl()
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| D | sfn_emittexinstruction.cpp | 62 case nir_texop_tg4: in do_emit()
94 case nir_texop_tg4: in do_emit()
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| /external/mesa3d/src/panfrost/midgard/ |
| D | midgard_compile.c | 1895 if (instr->op == nir_texop_tg4 && instr->is_shadow) in mdg_texture_mode()
1897 else if (instr->op == nir_texop_tg4) in mdg_texture_mode()
1943 if (instr->is_shadow && !instr->is_new_style_shadow && instr->op != nir_texop_tg4) in emit_texop_native()
2113 case nir_texop_tg4: in emit_tex()
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| /external/mesa3d/src/compiler/spirv/ |
| D | spirv_to_nir.c | 2599 texop = nir_texop_tg4; in vtn_handle_texture()
2648 case nir_texop_tg4: in vtn_handle_texture()
2781 texop == nir_texop_tg4); in vtn_handle_texture()
2791 texop == nir_texop_txs || texop == nir_texop_tg4); in vtn_handle_texture()
2825 vtn_assert(texop == nir_texop_tg4); in vtn_handle_texture()
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| /external/mesa3d/src/intel/compiler/ |
| D | brw_vec4_nir.cpp | 1938 case nir_texop_tg4: op = ir_tg4; break; in ir_texture_opcode_for_nir_texop()
2091 if (instr->op == nir_texop_tg4) { in nir_emit_texture()
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| D | brw_fs_nir.cpp | 5864 case nir_texop_tg4: in nir_emit_texture()
5896 if (instr->op == nir_texop_tg4) { in nir_emit_texture()
5914 instr->op != nir_texop_tg4 && instr->op != nir_texop_query_levels) { in nir_emit_texture()
5928 if (instr->op == nir_texop_tg4 && devinfo->gen == 6) in nir_emit_texture()
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| /external/mesa3d/src/gallium/auxiliary/nir/ |
| D | nir_to_tgsi.c | 1789 case nir_texop_tg4: in ntt_emit_texture()
1910 if (instr->op == nir_texop_tg4 && target != TGSI_TEXTURE_SHADOWCUBE_ARRAY) { in ntt_emit_texture()
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| /external/mesa3d/src/gallium/drivers/nouveau/codegen/ |
| D | nv50_ir_from_nir.cpp | 514 case nir_texop_tg4: in getOperation()
2934 case nir_texop_tg4: in visit()
3044 case nir_texop_tg4: in visit()
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| /external/mesa3d/src/gallium/auxiliary/gallivm/ |
| D | lp_bld_nir.c | 1853 else if (instr->op == nir_texop_tg4) { in visit_tex()
1969 if (instr->op == nir_texop_tex || instr->op == nir_texop_tg4 || instr->op == nir_texop_txb || in visit_tex()
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| /external/mesa3d/src/intel/vulkan/ |
| D | anv_nir_apply_pipeline_layout.c | 1000 tex->op == nir_texop_tg4 || /* We can't swizzle TG4 */ in lower_gen7_tex_swizzle()
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| /external/mesa3d/src/amd/llvm/ |
| D | ac_nir_to_llvm.c | 1438 case nir_texop_tg4: in build_tex_intrinsic()
1455 if (instr->op == nir_texop_tg4 && ctx->ac.chip_class <= GFX8) { in build_tex_intrinsic()
4323 if (instr->op == nir_texop_tg4) { in visit_tex()
4357 instr->op != nir_texop_lod && instr->op != nir_texop_tg4) in visit_tex()
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| /external/mesa3d/src/panfrost/bifrost/ |
| D | bifrost_compile.c | 1805 case nir_texop_tg4: in bi_tex_op()
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| /external/mesa3d/src/compiler/glsl/ |
| D | glsl_to_nir.cpp | 2401 op = nir_texop_tg4; in visit()
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| /external/mesa3d/src/amd/compiler/ |
| D | aco_instruction_selection.cpp | 8668 bool tg4_integer_workarounds = ctx->options->chip_class <= GFX8 && instr->op == nir_texop_tg4 && in visit_tex()
8897 if (instr->op == nir_texop_tg4) { in visit_tex()
9210 if (instr->op == nir_texop_tg4) { in visit_tex()
9282 unsigned mask = instr->op == nir_texop_tg4 ? 0xF : dmask; in visit_tex()
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