| /external/libunwind/include/tdep-ia64/ |
| D | rse.h | 58 rse_skip_regs (uint64_t addr, long num_regs) in rse_skip_regs() argument
60 long delta = rse_slot_num(addr) + num_regs; in rse_skip_regs()
62 if (num_regs < 0) in rse_skip_regs()
64 return addr + ((num_regs + delta/0x3f) << 3); in rse_skip_regs()
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| /external/libunwind/src/ia64/ |
| D | Gstep.c | 70 unw_word_t sc_addr, num_regs; in linux_interrupt()
76 num_regs = c->cfm & 0x7f; in linux_interrupt()
78 num_regs = 0; in linux_interrupt()
87 *num_regsp = num_regs; /* size of frame */ in linux_interrupt()
224 unw_word_t prev_ip, prev_sp, prev_bsp, ip, num_regs; in update_frame_state() local
265 num_regs = 0; in update_frame_state()
274 if ((ret = linux_sigtramp (c, prev_cfm_loc, &num_regs)) < 0) in update_frame_state()
281 if ((ret = linux_interrupt (c, prev_cfm_loc, &num_regs, in update_frame_state()
288 if ((ret = hpux_sigtramp (c, prev_cfm_loc, &num_regs)) < 0) in update_frame_state()
311 num_regs = (c->cfm >> 7) & 0x7f; /* size of locals */ in update_frame_state()
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| D | Gscript.c | 396 int r, i, j, max, max_reg, max_when, num_regs = 0; in sort_regs() local
406 regorder[num_regs++] = r; in sort_regs()
413 for (i = max = 0; i < num_regs - 1; ++i) in sort_regs()
418 for (j = i + 1; j < num_regs; ++j) in sort_regs()
431 return num_regs; in sort_regs()
440 int num_regs, i, ret, regorder[IA64_NUM_PREGS - 3]; in build_script() local
491 num_regs = sort_regs (&sr, regorder); in build_script()
492 for (i = 0; i < num_regs; ++i) in build_script()
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| /external/ethtool/ |
| D | vioc.c | 18 unsigned int num_regs; in vioc_dump_regs() local
27 num_regs = regs->len/VIOC_REGS_LINE_SIZE; in vioc_dump_regs()
29 for (i = 0; i < num_regs; i++){ in vioc_dump_regs()
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| /external/mesa3d/src/gallium/auxiliary/util/ |
| D | u_simple_shaders.c | 1079 unsigned num_regs; in util_make_tess_ctrl_passthrough_shader() local
1094 num_regs = 0; in util_make_tess_ctrl_passthrough_shader()
1111 dst[num_regs] = ureg_DECL_output(ureg, in util_make_tess_ctrl_passthrough_shader()
1114 src[num_regs] = ureg_DECL_input(ureg, vs_semantic_names[j], in util_make_tess_ctrl_passthrough_shader()
1120 src[num_regs] = ureg_src_dimension(src[num_regs], 0); in util_make_tess_ctrl_passthrough_shader()
1121 dst[num_regs] = ureg_dst_dimension(dst[num_regs], 0); in util_make_tess_ctrl_passthrough_shader()
1124 num_regs++; in util_make_tess_ctrl_passthrough_shader()
1134 dst[num_regs] = ureg_DECL_output(ureg, TGSI_SEMANTIC_TESSOUTER, in util_make_tess_ctrl_passthrough_shader()
1135 num_regs); in util_make_tess_ctrl_passthrough_shader()
1136 src[num_regs] = ureg_DECL_constant(ureg, 0); in util_make_tess_ctrl_passthrough_shader()
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| /external/arm-trusted-firmware/include/lib/el3_runtime/aarch32/ |
| D | context.h | 38 #define DEFINE_REG_STRUCT(name, num_regs) \ argument
40 uint32_t _regs[num_regs]; \
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| /external/u-boot/drivers/reset/ |
| D | reset-mediatek.c | 77 int mediatek_reset_bind(struct udevice *pdev, u32 regofs, u32 num_regs) in mediatek_reset_bind() argument
90 priv->nr_resets = num_regs * 32; in mediatek_reset_bind()
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| /external/u-boot/arch/arm/include/asm/arch-mediatek/ |
| D | reset.h | 11 int mediatek_reset_bind(struct udevice *pdev, u32 regofs, u32 num_regs);
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| /external/igt-gpu-tools/assembler/ |
| D | brw_eu.h | 298 int num_regs,
303 int num_regs,
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| D | brw_eu_emit.c | 1895 int num_regs, in brw_oword_block_write_scratch() argument
1907 if (num_regs == 1) { in brw_oword_block_write_scratch()
2007 int num_regs, in brw_oword_block_read_scratch() argument
2020 if (num_regs == 1) { in brw_oword_block_read_scratch()
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| /external/mesa3d/src/intel/compiler/ |
| D | brw_wm_iz.cpp | 168 payload.num_regs = reg; in setup_fs_payload_gen4()
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| D | brw_eu_emit.c | 588 unsigned num_regs, in gen7_set_dp_scratch_message() argument
595 assert(num_regs == 1 || num_regs == 2 || num_regs == 4 || in gen7_set_dp_scratch_message()
596 (devinfo->gen >= 8 && num_regs == 8)); in gen7_set_dp_scratch_message()
597 const unsigned block_size = (devinfo->gen >= 8 ? util_logbase2(num_regs) : in gen7_set_dp_scratch_message()
598 num_regs - 1); in gen7_set_dp_scratch_message()
2101 int num_regs, in brw_oword_block_write_scratch() argument
2117 const unsigned mlen = 1 + num_regs; in brw_oword_block_write_scratch()
2196 BRW_DATAPORT_OWORD_BLOCK_DWORDS(num_regs * 8), in brw_oword_block_write_scratch()
2214 int num_regs, in brw_oword_block_read_scratch() argument
2237 const unsigned rlen = num_regs; in brw_oword_block_read_scratch()
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| D | brw_fs.cpp | 1648 struct brw_reg brw_reg = brw_vec1_grf(payload.num_regs + in assign_curb_setup()
1670 struct brw_reg mask = brw_vec1_grf(payload.num_regs + mask_param / 8, in assign_curb_setup()
1690 retype(brw_vec8_grf(payload.num_regs + i, 0), in assign_curb_setup()
1701 this->first_non_payload_grf = payload.num_regs + prog_data->curb_read_length; in assign_curb_setup()
1822 int urb_start = payload.num_regs + prog_data->base.curb_read_length; in assign_urb_setup()
1860 int grf = payload.num_regs + in convert_attr_sources_to_hw_regs()
7439 payload.num_regs++; in setup_fs_payload_gen6()
7443 payload.subspan_coord_reg[j] = payload.num_regs++; in setup_fs_payload_gen6()
7456 payload.barycentric_coord_reg[i][j] = payload.num_regs; in setup_fs_payload_gen6()
7457 payload.num_regs += payload_width / 4; in setup_fs_payload_gen6()
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| D | brw_eu.h | 1143 int num_regs,
1148 int num_regs,
1153 int num_regs,
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| D | brw_vec4.cpp | 2012 const unsigned num_regs = DIV_ROUND_UP(size_written, REG_SIZE); in fixup_3src_null_dest() local
2014 inst->dst = retype(dst_reg(VGRF, alloc.allocate(num_regs)), in fixup_3src_null_dest()
2300 unsigned num_regs = DIV_ROUND_UP(size_written, REG_SIZE); in lower_simd_width() local
2301 dst = retype(dst_reg(VGRF, alloc.allocate(num_regs)), in lower_simd_width()
2952 prog_data->base.base.dispatch_grf_start_reg = v.payload.num_regs; in brw_compile_vs()
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| D | brw_vec4_tcs.cpp | 466 prog_data->base.base.dispatch_grf_start_reg = v.payload.num_regs; in brw_compile_tcs()
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| D | brw_vec4_gs_visitor.cpp | 823 prog_data->base.base.dispatch_grf_start_reg = v.payload.num_regs; in brw_compile_gs()
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| D | brw_fs.h | 400 uint8_t num_regs; member
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| /external/arm-trusted-firmware/include/lib/el3_runtime/aarch64/ |
| D | context.h | 231 #define DEFINE_REG_STRUCT(name, num_regs) \ argument
233 uint64_t _regs[num_regs]; \
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| /external/mesa3d/src/gallium/drivers/nouveau/nv30/ |
| D | nvfx_fragprog.c | 32 int num_regs; member
178 if (fpc->num_regs < (dst.index + 1)) in emit_dst()
179 fpc->num_regs = dst.index + 1; in emit_dst()
1081 fpc->num_regs = 2; in _nvfx_fragprog_translate()
1125 fp->fp_control |= (fpc->num_regs-1)/2; in _nvfx_fragprog_translate()
1127 fp->fp_control |= fpc->num_regs << NV40_3D_FP_CONTROL_TEMP_COUNT__SHIFT; in _nvfx_fragprog_translate()
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| /external/v8/src/compiler/backend/ |
| D | register-allocator.cc | 1938 int num_regs = config()->num_double_registers(); in FixedFPLiveRangeFor() local
1944 num_regs = config()->num_float_registers(); in FixedFPLiveRangeFor()
1948 num_regs = config()->num_simd128_registers(); in FixedFPLiveRangeFor()
1956 int offset = spill_mode == SpillMode::kSpillAtDefinition ? 0 : num_regs; in FixedFPLiveRangeFor()
1958 DCHECK(index < num_regs); in FixedFPLiveRangeFor()
1959 USE(num_regs); in FixedFPLiveRangeFor()
3281 int num_regs = num_registers(); in ComputeStateFromManyPredecessors() local
3287 GetFPRegisterSet(rep, &num_regs, &num_codes, &codes); in ComputeStateFromManyPredecessors()
3288 for (int idx = 0; idx < num_regs; idx++) { in ComputeStateFromManyPredecessors()
3871 int* num_regs, int* num_codes, in GetFPRegisterSet() argument
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| /external/kernel-headers/original/uapi/sound/ |
| D | asoc.h | 441 __le32 num_regs; member
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| /external/v8/src/execution/ppc/ |
| D | simulator-ppc.h | 236 void ProcessPUW(Instruction* instr, int num_regs, int operand_size,
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| /external/v8/src/execution/arm/ |
| D | simulator-arm.cc | 1440 int32_t Simulator::ProcessPU(Instruction* instr, int num_regs, int reg_size, in ProcessPU() argument
1451 *end_address = rn_val + (num_regs * reg_size) - reg_size; in ProcessPU()
1452 rn_val = rn_val + (num_regs * reg_size); in ProcessPU()
1456 *start_address = rn_val - (num_regs * reg_size); in ProcessPU()
1463 *end_address = rn_val + (num_regs * reg_size); in ProcessPU()
1477 int num_regs = count_bits(rlist); in HandleRList() local
1482 ProcessPU(instr, num_regs, kPointerSize, &start_address, &end_address); in HandleRList()
1515 int num_regs; in HandleVList() local
1518 num_regs = instr->Immed8Value(); in HandleVList()
1520 num_regs = instr->Immed8Value() / 2; in HandleVList()
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| D | simulator-arm.h | 328 int32_t ProcessPU(Instruction* instr, int num_regs, int operand_size,
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