/external/tensorflow/tensorflow/core/distributed_runtime/ |
D | rpcbench_test.cc | 124 GraphDef CreateGraphDef(int num_stages, int width, int tensor_size, in CreateGraphDef() argument 138 for (int i = 0; i < num_stages; i++) { in CreateGraphDef() 169 static void BM_Helper(int iters, int width, int num_stages, int tensor_size, in BM_Helper() argument 176 GraphDef def = CreateGraphDef(num_stages, width, tensor_size, in BM_Helper() 215 static void BM_ShardedProgram(int iters, int width, int num_stages) { in BM_ShardedProgram() argument 216 BM_Helper(iters, width, num_stages, 2 /*tensor_size*/, true /*multi-device*/); in BM_ShardedProgram() 240 static void BM_SingleDevice(int iters, int width, int num_stages) { in BM_SingleDevice() argument 241 BM_Helper(iters, width, num_stages, 2 /*tensor_size*/, in BM_SingleDevice()
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/external/mesa3d/src/gallium/frontends/nine/ |
D | nine_ff.h | 65 nine_ff_get_projected_key(struct nine_context *context, unsigned num_stages) in nine_ff_get_projected_key() argument 69 char input_texture_coord[num_stages]; in nine_ff_get_projected_key() 77 if (s < num_stages) in nine_ff_get_projected_key() 83 for (s = 0; s < num_stages; ++s) { in nine_ff_get_projected_key()
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/external/tensorflow/tensorflow/core/grappler/inputs/ |
D | trivial_test_graph_input_yielder.cc | 31 GraphDef CreateGraphDef(int num_stages, int width, int tensor_size, in CreateGraphDef() argument 46 for (int i = 0; i < num_stages; i++) { in CreateGraphDef() 90 int num_stages, int width, int tensor_size, bool insert_queue, in TrivialTestGraphInputYielder() argument 92 : num_stages_(num_stages), in TrivialTestGraphInputYielder()
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D | trivial_test_graph_input_yielder.h | 31 TrivialTestGraphInputYielder(int num_stages, int width, int tensor_size,
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/external/mesa3d/src/gallium/drivers/zink/ |
D | zink_pipeline.c | 152 uint32_t num_stages = 0; in zink_create_gfx_pipeline() local 162 shader_stages[num_stages++] = stage; in zink_create_gfx_pipeline() 164 assert(num_stages > 0); in zink_create_gfx_pipeline() 167 pci.stageCount = num_stages; in zink_create_gfx_pipeline()
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/external/mesa3d/src/mesa/drivers/dri/i965/ |
D | brw_context.c | 463 unsigned num_stages = 0; in brw_initialize_context_constants() local 466 num_stages++; in brw_initialize_context_constants() 547 ctx->Const.MaxUniformBufferBindings = num_stages * BRW_MAX_UBO; in brw_initialize_context_constants() 548 ctx->Const.MaxCombinedUniformBlocks = num_stages * BRW_MAX_UBO; in brw_initialize_context_constants() 549 ctx->Const.MaxCombinedAtomicBuffers = num_stages * BRW_MAX_ABO; in brw_initialize_context_constants() 550 ctx->Const.MaxCombinedShaderStorageBlocks = num_stages * BRW_MAX_SSBO; in brw_initialize_context_constants() 551 ctx->Const.MaxShaderStorageBufferBindings = num_stages * BRW_MAX_SSBO; in brw_initialize_context_constants() 552 ctx->Const.MaxCombinedTextureImageUnits = num_stages * max_samplers; in brw_initialize_context_constants() 553 ctx->Const.MaxCombinedImageUniforms = num_stages * BRW_MAX_IMAGES; in brw_initialize_context_constants()
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/external/tensorflow/tensorflow/compiler/xla/service/gpu/ |
D | ir_emitter_unnested.cc | 1060 int64 num_stages = tensorflow::Log2Ceiling(dimension_to_sort_bound); in HandleSort() local 1061 CHECK_GE(1ULL << num_stages, dimension_to_sort_bound); in HandleSort() 1062 CHECK_LT(1ULL << (num_stages - 1), dimension_to_sort_bound); in HandleSort() 1088 const uint64 kTileSize = std::min(2048ULL, 1ULL << num_stages); in HandleSort() 1096 uint64 standard_num_iterations_in_sort_dim = 1ULL << (num_stages - 1); in HandleSort() 1166 for (int64 stage = 0; stage < num_stages; ++stage) { in HandleSort()
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/external/mesa3d/src/intel/vulkan/ |
D | genX_cmd_buffer.c | 2470 const unsigned num_stages = in cmd_buffer_alloc_push_constants() local 2472 unsigned size_per_stage = push_constant_kb / num_stages; in cmd_buffer_alloc_push_constants()
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