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Searched refs:operand0 (Results 1 – 17 of 17) sorted by relevance

/external/igt-gpu-tools/lib/
Di915_3d.h389 #define i915_fs_arith_masked(op, dest_reg, dest_mask, operand0, operand1, operand2) \ argument
390 _i915_fs_arith_masked(A0_##op, dest_reg, dest_mask, operand0, operand1, operand2)
392 #define i915_fs_arith(op, dest_reg, operand0, operand1, operand2) \ argument
393 _i915_fs_arith(A0_##op, dest_reg, operand0, operand1, operand2)
395 #define _i915_fs_arith_masked(cmd, dest_reg, dest_mask, operand0, operand1, operand2) \ argument
404 (REG_TYPE(operand0) << A0_SRC0_TYPE_SHIFT) | \
405 (REG_NR(operand0) << A0_SRC0_NR_SHIFT)); \
406 OUT_BATCH(i915_get_hardware_channel_val(REG_X(operand0), \
409 i915_get_hardware_channel_val(REG_Y(operand0), \
412 i915_get_hardware_channel_val(REG_Z(operand0), \
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/external/v8/src/interpreter/
Dbytecode-node.h30 V8_INLINE BytecodeNode(Bytecode bytecode, uint32_t operand0,
37 SetOperand(0, operand0); in bytecode_()
40 V8_INLINE BytecodeNode(Bytecode bytecode, uint32_t operand0,
48 SetOperand(0, operand0); in bytecode_()
52 V8_INLINE BytecodeNode(Bytecode bytecode, uint32_t operand0,
60 SetOperand(0, operand0); in bytecode_()
65 V8_INLINE BytecodeNode(Bytecode bytecode, uint32_t operand0,
74 SetOperand(0, operand0); in bytecode_()
80 V8_INLINE BytecodeNode(Bytecode bytecode, uint32_t operand0,
89 SetOperand(0, operand0); in bytecode_()
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Dbytecode-array-builder.cc205 uint32_t operand0 = static_cast<uint32_t>(src.ToOperand()); in OutputMovRaw() local
208 BytecodeNode::Mov(BytecodeSourceInfo(), operand0, operand1)); in OutputMovRaw()
/external/mesa3d/src/gallium/drivers/svga/
Dsvga_tgsi_vgpu10.c1094 VGPU10OperandToken0 operand0, in setup_operand0_indexing() argument
1105 if (operand0.operandType == VGPU10_OPERAND_TYPE_IMMEDIATE32 || in setup_operand0_indexing()
1106 operand0.operandType == VGPU10_OPERAND_TYPE_INPUT_PRIMITIVEID || in setup_operand0_indexing()
1107 operand0.operandType == VGPU10_OPERAND_TYPE_INPUT_GS_INSTANCE_ID || in setup_operand0_indexing()
1108 operand0.operandType == VGPU10_OPERAND_TYPE_INPUT_THREAD_ID || in setup_operand0_indexing()
1109 operand0.operandType == VGPU10_OPERAND_TYPE_INPUT_THREAD_ID_IN_GROUP || in setup_operand0_indexing()
1110 operand0.operandType == VGPU10_OPERAND_TYPE_OUTPUT_CONTROL_POINT_ID) { in setup_operand0_indexing()
1113 assert(operand0.selectionMode == 0); in setup_operand0_indexing()
1115 else if (operand0.operandType == VGPU10_OPERAND_TYPE_INPUT_DOMAIN_POINT) { in setup_operand0_indexing()
1143 operand0.indexDimension = indexDim; in setup_operand0_indexing()
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/external/tensorflow/tensorflow/compiler/xla/service/gpu/
Dfusion_merger_test.cc93 auto* operand0 = root->operand(0); in TEST_F() local
94 EXPECT_EQ(HloOpcode::kFusion, operand0->opcode()); in TEST_F()
95 EXPECT_EQ(4, operand0->fused_instruction_count()); in TEST_F()
/external/v8/src/compiler/backend/ia32/
Dinstruction-selector-ia32.cc248 InstructionOperand operand0 = g.UseRegister(node->InputAt(0)); in VisitRROFloat() local
251 selector->Emit(avx_opcode, g.DefineAsRegister(node), operand0, operand1); in VisitRROFloat()
253 selector->Emit(sse_opcode, g.DefineSameAsFirst(node), operand0, operand1); in VisitRROFloat()
273 InstructionOperand operand0 = g.UseRegister(node->InputAt(0)); in VisitRRSimd() local
275 selector->Emit(avx_opcode, g.DefineAsRegister(node), operand0); in VisitRRSimd()
277 selector->Emit(sse_opcode, g.DefineSameAsFirst(node), operand0); in VisitRRSimd()
288 InstructionOperand operand0 = g.UseRegister(node->InputAt(0)); in VisitRROSimd() local
290 selector->Emit(avx_opcode, g.DefineAsRegister(node), operand0, in VisitRROSimd()
293 selector->Emit(sse_opcode, g.DefineSameAsFirst(node), operand0, in VisitRROSimd()
301 InstructionOperand operand0 = g.UseRegister(node->InputAt(0)); in VisitRRISimd() local
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/external/mesa3d/src/gallium/drivers/zink/nir_to_spirv/
Dspirv_builder.h181 SpvId operand0, SpvId operand1);
185 SpvId operand0, SpvId operand1, SpvId operand2);
189 SpvId operand0, SpvId operand1, SpvId operand2, SpvId operand3);
Dspirv_builder.c420 SpvId operand0, SpvId operand1) in spirv_builder_emit_binop() argument
427 spirv_buffer_emit_word(&b->instructions, operand0); in spirv_builder_emit_binop()
434 SpvId operand0, SpvId operand1, SpvId operand2) in spirv_builder_emit_triop() argument
441 spirv_buffer_emit_word(&b->instructions, operand0); in spirv_builder_emit_triop()
449 SpvId operand0, SpvId operand1, SpvId operand2, SpvId operand3) in spirv_builder_emit_quadop() argument
456 spirv_buffer_emit_word(&b->instructions, operand0); in spirv_builder_emit_quadop()
/external/tensorflow/tensorflow/compiler/mlir/lite/ir/
Dtfl_ops.cc707 Value operand0 = op.getOperand(0); in Verify() local
708 auto input_type = operand0.getType().cast<ShapedType>(); in Verify()
/external/tensorflow/tensorflow/compiler/mlir/lite/transforms/
Doptimize_patterns.td388 // Checks if the operand0's rank is one less than operand1's rank.
/external/v8/src/compiler/backend/arm/
Dinstruction-selector-arm.cc2737 InstructionOperand operand0 = g.UseRegister(node->InputAt(0)); local
2739 Emit(kArmI64x2SplatI32Pair, g.DefineAsRegister(node), operand0, operand1);
/external/tensorflow/tensorflow/compiler/xla/service/
Dhlo_evaluator_test.cc117 auto operand0 = in TestTernaryOp() local
124 expected.shape(), opcode, operand0, operand1, operand2)); in TestTernaryOp()
/external/tensorflow/tensorflow/compiler/xla/g3doc/
Doperation_semantics.md2680 For example, if there are three operands `operand0 = [3, 1]`,
2682 only the values of `operand0` with less-than, then the output of the sort is the
/external/swiftshader/third_party/llvm-7.0/llvm/docs/
DAMDGPUUsage.rst4095 *<opcode> <operand0>, <operand1>,... <modifier0> <modifier1>...*
/external/toolchain-utils/deprecated/dejagnu/gdb_baseline/
Dx86_64-cros-linux-gnu16569 PASS: gdb.opt/clobbered-registers-O2.exp: print operand0
Darmv7a-cros-linux-gnueabi16199 PASS: gdb.opt/clobbered-registers-O2.exp: print operand0
Di686-pc-linux-gnu16301 PASS: gdb.opt/clobbered-registers-O2.exp: print operand0