| /external/swiftshader/third_party/llvm-7.0/llvm/test/MC/AArch64/SVE/ |
| D | orr.s | 12 orr z5.b, z5.b, #0xf9 label
18 orr z23.h, z23.h, #0xfff9 label
24 orr z0.s, z0.s, #0xfffffff9 label
30 orr z0.d, z0.d, #0xfffffffffffffff9 label
36 orr z5.b, z5.b, #0x6 label
42 orr z23.h, z23.h, #0x6 label
48 orr z0.s, z0.s, #0x6 label
54 orr z0.d, z0.d, #0x6 label
60 orr z0.d, z0.d, z0.d // should use mov-alias label
66 orr z23.d, z13.d, z8.d // should not use mov-alias label
[all …]
|
| D | orr-diagnostics.s | 6 orr z5.b, z5.b, #0xfa label
11 orr z5.b, z5.b, #0xfff9 label
16 orr z5.h, z5.h, #0xfffa label
21 orr z5.h, z5.h, #0xfffffff9 label
26 orr z5.s, z5.s, #0xfffffffa label
31 orr z5.s, z5.s, #0xffffffffffffff9 label
36 orr z15.d, z15.d, #0xfffffffffffffffa label
44 orr z7.d, z8.d, #254 label
49 orr z0.d, p0/m, z1.d, z2.d label
55 orr z21.d, z5.d, z26.b label
[all …]
|
| /external/capstone/suite/MC/AArch64/ |
| D | neon-mov.s.cs | 41 0x20,0x14,0x00,0x0f = orr v0.2s, #0x1
42 0x01,0x14,0x00,0x0f = orr v1.2s, #0x0
43 0x20,0x34,0x00,0x0f = orr v0.2s, #0x1, lsl #8
44 0x20,0x54,0x00,0x0f = orr v0.2s, #0x1, lsl #16
45 0x20,0x74,0x00,0x0f = orr v0.2s, #0x1, lsl #24
46 0x20,0x14,0x00,0x4f = orr v0.4s, #0x1
47 0x20,0x34,0x00,0x4f = orr v0.4s, #0x1, lsl #8
48 0x20,0x54,0x00,0x4f = orr v0.4s, #0x1, lsl #16
49 0x20,0x74,0x00,0x4f = orr v0.4s, #0x1, lsl #24
50 0x3f,0x94,0x00,0x0f = orr v31.4h, #0x1
[all …]
|
| /external/llvm/test/MC/AArch64/ |
| D | neon-mov.s | 102 orr v0.2s, #1
103 orr v1.2s, #0
104 orr v0.2s, #1, lsl #8
105 orr v0.2s, #1, lsl #16
106 orr v0.2s, #1, lsl #24
107 orr v0.4s, #1
108 orr v0.4s, #1, lsl #8
109 orr v0.4s, #1, lsl #16
110 orr v0.4s, #1, lsl #24
111 orr v31.4h, #1
[all …]
|
| D | arm64-aliases.s | 27 orr x2, xzr, x9
29 orr w2, wzr, w9
190 orr x20, xzr, #0xaaaaaaaaaaaaaaaa
191 orr w15, wzr, #0xaaaaaaaa
198 orr x3, xzr, #0x1
199 orr w3, wzr, #0x1
200 orr x3, xzr, #0x10000
201 orr w3, wzr, #0x10000
202 orr x3, xzr, #0x700000000
203 orr x3, xzr, #0x3000000000000
[all …]
|
| D | arm64-logical-encoding.s | 34 orr w1, w2, #0x4000
35 orr x1, x2, #0x8000
37 ; CHECK: orr w1, w2, #0x4000 ; encoding: [0x41,0x00,0x12,0x32]
38 ; CHECK: orr x1, x2, #0x8000 ; encoding: [0x41,0x00,0x71,0xb2]
40 orr w8, wzr, #0x1
41 orr x8, xzr, #0x1
43 ; CHECK: orr w8, wzr, #0x1 ; encoding: [0xe8,0x03,0x00,0x32]
44 ; CHECK: orr x8, xzr, #0x1 ; encoding: [0xe8,0x03,0x40,0xb2]
182 orr w1, w2, w3
183 orr x1, x2, x3
[all …]
|
| /external/swiftshader/third_party/llvm-7.0/llvm/test/MC/AArch64/ |
| D | neon-mov.s | 102 orr v0.2s, #1
103 orr v1.2s, #0
104 orr v0.2s, #1, lsl #8
105 orr v0.2s, #1, lsl #16
106 orr v0.2s, #1, lsl #24
107 orr v0.4s, #1
108 orr v0.4s, #1, lsl #8
109 orr v0.4s, #1, lsl #16
110 orr v0.4s, #1, lsl #24
111 orr v31.4h, #1
[all …]
|
| D | arm64-aliases.s | 27 orr x2, xzr, x9
29 orr w2, wzr, w9
190 orr x20, xzr, #0xaaaaaaaaaaaaaaaa
191 orr w15, wzr, #0xaaaaaaaa
198 orr x3, xzr, #0x1
199 orr w3, wzr, #0x1
200 orr x3, xzr, #0x10000
201 orr w3, wzr, #0x10000
202 orr x3, xzr, #0x700000000
203 orr x3, xzr, #0x3000000000000
[all …]
|
| D | arm64-logical-encoding.s | 34 orr w1, w2, #0x4000
35 orr x1, x2, #0x8000
37 ; CHECK: orr w1, w2, #0x4000 ; encoding: [0x41,0x00,0x12,0x32]
38 ; CHECK: orr x1, x2, #0x8000 ; encoding: [0x41,0x00,0x71,0xb2]
40 orr w8, wzr, #0x1
41 orr x8, xzr, #0x1
43 ; CHECK: orr w8, wzr, #0x1 ; encoding: [0xe8,0x03,0x00,0x32]
44 ; CHECK: orr x8, xzr, #0x1 ; encoding: [0xe8,0x03,0x40,0xb2]
182 orr w1, w2, w3
183 orr x1, x2, x3
[all …]
|
| /external/swiftshader/third_party/llvm-7.0/llvm/test/CodeGen/ARM/ |
| D | illegal-bitfield-loadstore.ll | 9 ; LE-NEXT: orr r1, r1, #384
17 ; BE-NEXT: orr r1, r2, r1, lsl #8
18 ; BE-NEXT: orr r1, r1, #384
34 ; LE-NEXT: orr r2, r2, #49152
35 ; LE-NEXT: orr r1, r1, #384
45 ; BE-NEXT: orr r1, r1, #1
60 ; LE-NEXT: orr r3, r3, #57088
62 ; LE-NEXT: orr r1, r2, r1, lsl #13
70 ; BE-NEXT: orr r3, r3, #16711680
72 ; BE-NEXT: orr r1, r2, r1, lsl #13
[all …]
|
| /external/arm-optimized-routines/string/aarch64/ |
| D | strcpy.S | 114 orr tmp2, tmp2, #REP8_7f
119 orr tmp4, tmp4, #REP8_7f
122 orr tmp2, data1, #REP8_7f
126 orr tmp4, data2, #REP8_7f
208 orr tmp2, data1, #REP8_7f
210 orr tmp4, data2, #REP8_7f
228 orr tmp2, data1, #REP8_7f
261 orr data1, data1, tmp2
262 orr data2a, data2, tmp2
267 orr tmp2, data1, #REP8_7f
[all …]
|
| D | strlen.S | 91 orr tmp2, data1, REP8_7f
93 orr tmp4, data2, REP8_7f
120 orr tmp2, tmp1, tmp3
126 orr tmp2, tmp1, tmp3
132 orr tmp2, data1, REP8_7f
133 orr tmp4, data2, REP8_7f
149 orr tmp2, data1, REP8_7f
165 orr tmp2, data1, REP8_7f
167 orr tmp4, data2, REP8_7f
174 orr tmp2, data1, REP8_7f
[all …]
|
| /external/swiftshader/third_party/llvm-7.0/llvm/test/CodeGen/AArch64/ |
| D | movw-consts.ll | 12 ; CHECK: orr w0, wzr, #0x1
18 ; CHECK: orr w0, wzr, #0xffff
24 ; CHECK: orr w0, wzr, #0x10000
30 ; CHECK: orr w0, wzr, #0xffff0000
36 ; CHECK: orr x0, xzr, #0x100000000
42 ; CHECK: orr x0, xzr, #0xffff00000000
48 ; CHECK: orr x0, xzr, #0x1000000000000
85 ; CHECK: orr {{w[0-9]+}}, wzr, #0x1
92 ; CHECK: orr {{w[0-9]+}}, wzr, #0xffff
99 ; CHECK: orr {{w[0-9]+}}, wzr, #0x10000
[all …]
|
| D | arm64-patchpoint-webkit_jscc.ll | 41 ; CHECK: orr w[[REG:[0-9]+]], wzr, #0x6
43 ; CHECK-NEXT: orr w[[REG:[0-9]+]], wzr, #0x4
45 ; CHECK-NEXT: orr w[[REG:[0-9]+]], wzr, #0x2
53 ; FAST: orr [[REG1:x[0-9]+]], xzr, #0x2
55 ; FAST-NEXT: orr [[REG2:w[0-9]+]], wzr, #0x4
57 ; FAST-NEXT: orr [[REG3:x[0-9]+]], xzr, #0x6
75 ; CHECK-NEXT: orr w[[REG:[0-9]+]], wzr, #0x8
77 ; CHECK-NEXT: orr w[[REG:[0-9]+]], wzr, #0x6
79 ; CHECK-NEXT: orr w[[REG:[0-9]+]], wzr, #0x4
81 ; CHECK-NEXT: orr w[[REG:[0-9]+]], wzr, #0x2
[all …]
|
| /external/llvm/test/CodeGen/AArch64/ |
| D | movw-consts.ll | 12 ; CHECK: orr w0, wzr, #0x1
18 ; CHECK: orr w0, wzr, #0xffff
24 ; CHECK: orr w0, wzr, #0x10000
30 ; CHECK: orr w0, wzr, #0xffff0000
36 ; CHECK: orr x0, xzr, #0x100000000
42 ; CHECK: orr x0, xzr, #0xffff00000000
48 ; CHECK: orr x0, xzr, #0x1000000000000
85 ; CHECK: orr {{w[0-9]+}}, wzr, #0x1
92 ; CHECK: orr {{w[0-9]+}}, wzr, #0xffff
99 ; CHECK: orr {{w[0-9]+}}, wzr, #0x10000
[all …]
|
| D | arm64-patchpoint-webkit_jscc.ll | 44 ; CHECK: orr w[[REG:[0-9]+]], wzr, #0x6
46 ; CHECK-NEXT: orr w[[REG:[0-9]+]], wzr, #0x4
48 ; CHECK-NEXT: orr w[[REG:[0-9]+]], wzr, #0x2
57 ; FAST: orr [[REG1:x[0-9]+]], xzr, #0x2
58 ; FAST-NEXT: orr [[REG2:w[0-9]+]], wzr, #0x4
59 ; FAST-NEXT: orr [[REG3:x[0-9]+]], xzr, #0x6
80 ; CHECK-NEXT: orr w[[REG:[0-9]+]], wzr, #0x8
82 ; CHECK-NEXT: orr w[[REG:[0-9]+]], wzr, #0x6
84 ; CHECK-NEXT: orr w[[REG:[0-9]+]], wzr, #0x4
86 ; CHECK-NEXT: orr w[[REG:[0-9]+]], wzr, #0x2
[all …]
|
| /external/u-boot/arch/arm/mach-orion5x/ |
| D | lowlevel_init.S | 172 orr r0, r0, #SDRAM_PAD_CTRL_WR_EN
184 orr r1, r1, r1, LSL #6 /* r1[11:6]<DrvP> = r1[5:0]<DrvN> */
187 orr r0, r0, r1
194 orr r0, r0, #SDRAM_PAD_CTRL_WR_EN
206 orr r1, r1, r1, LSL #6 /* r1[5:0] = r3[22:17]<LockN> */
209 orr r0, r0, r1
220 orr r0, r0, #SDRAM_PAD_CTRL_WR_EN
226 orr r0, r0, r1
231 orr r0, r0, #SDRAM_PAD_CTRL_WR_EN
237 orr r0, r0, r1
[all …]
|
| /external/boringssl/linux-arm/crypto/fipsmodule/ |
| D | aes-armv4.S | 207 orr r0,r0,r4,lsl#8
209 orr r0,r0,r5,lsl#16
211 orr r0,r0,r6,lsl#24
214 orr r1,r1,r4,lsl#8
216 orr r1,r1,r5,lsl#16
218 orr r1,r1,r6,lsl#24
221 orr r2,r2,r4,lsl#8
223 orr r2,r2,r5,lsl#16
225 orr r2,r2,r6,lsl#24
228 orr r3,r3,r4,lsl#8
[all …]
|
| /external/boringssl/ios-arm/crypto/fipsmodule/ |
| D | aes-armv4.S | 208 orr r0,r0,r4,lsl#8
210 orr r0,r0,r5,lsl#16
212 orr r0,r0,r6,lsl#24
215 orr r1,r1,r4,lsl#8
217 orr r1,r1,r5,lsl#16
219 orr r1,r1,r6,lsl#24
222 orr r2,r2,r4,lsl#8
224 orr r2,r2,r5,lsl#16
226 orr r2,r2,r6,lsl#24
229 orr r3,r3,r4,lsl#8
[all …]
|
| /external/arm-trusted-firmware/lib/cpus/aarch64/ |
| D | cortex_a57.S | 33 orr x0, x0, #CORTEX_A57_ECTLR_DIS_TWD_ACC_PFTCH_BIT
35 orr x1, x1, #CORTEX_A57_ECTLR_L2_DPFTCH_DIST_MASK
89 orr x1, x1, #CORTEX_A57_CPUACTLR_EL1_NO_ALLOC_WBWA
131 orr x1, x1, #CORTEX_A57_CPUACTLR_EL1_DCC_AS_DCCI
158 orr x1, x1, #CORTEX_A57_CPUACTLR_EL1_DIS_DMB_NULLIFICATION
203 orr x1, x1, #CORTEX_A57_CPUACTLR_EL1_DIS_OVERREAD
230 orr x1, x1, #CORTEX_A57_CPUACTLR_EL1_DIS_LOAD_PASS_DMB
257 orr x1, x1, #CORTEX_A57_CPUACTLR_EL1_GRE_NGRE_AS_NGNRE
289 orr x1, x1, #CORTEX_A57_CPUACTLR_EL1_NO_ALLOC_WBWA
290 orr x1, x1, #(CORTEX_A57_CPUACTLR_EL1_DIS_L1_STREAMING | \
[all …]
|
| D | neoverse_n1.S | 94 orr x1, x1, NEOVERSE_N1_CPUACTLR_EL1_BIT_6
120 orr x1, x1, NEOVERSE_N1_CPUACTLR2_EL1_BIT_59
146 orr x1, x1, NEOVERSE_N1_CPUACTLR2_EL1_BIT_0
147 orr x1, x1, NEOVERSE_N1_CPUACTLR2_EL1_BIT_15
173 orr x1, x1, NEOVERSE_N1_CPUACTLR2_EL1_BIT_11
199 orr x1, x1, NEOVERSE_N1_WS_THR_L2_MASK
225 orr x1, x1, NEOVERSE_N1_CPUACTLR3_EL1_BIT_10
251 orr x1, x1, NEOVERSE_N1_CPUACTLR_EL1_BIT_13
277 orr x1, x1, NEOVERSE_N1_CPUECTLR_EL1_MM_TLBPF_DIS_BIT
303 orr x1, x1, NEOVERSE_N1_CPUACTLR_EL1_BIT_13
[all …]
|
| /external/u-boot/arch/arm/cpu/armv7/ |
| D | start.S | 61 orr r0, r0, #0xc0 @ disable FIQ and IRQ
156 orr r0, r0, #0x00000002 @ set bit 1 (--A-) Align
157 orr r0, r0, #0x00000800 @ set bit 11 (Z---) BTB
161 orr r0, r0, #0x00001000 @ set bit 12 (I) I-cache
167 orr r0, r0, #1 << 11 @ set bit #11
173 orr r0, r0, #1 << 4 @ set bit #4
179 orr r0, r0, #1 << 6 @ set bit #6
185 orr r0, r0, #1 << 11 @ set bit #11
190 orr r0, r0, #1 << 21 @ set bit #21
196 orr r0, r0, #1 << 22 @ set bit #22
[all …]
|
| /external/u-boot/board/armltd/integrator/ |
| D | lowlevel_init.S | 16 orr r1,r1,#CMMASK_RESET
45 orr r2,r2,#CMMASK_INIT_102
68 orr r2,r2,#CMMASK_CMxx6_COMMON
87 orr r1,r1,r2
160 orr r2, r1, r2, ASL#12 /* OR in column address lines */
161 orr r3, r2, r3, ASL#16 /* OR in number of banks */
162 orr r6, r6, r3 /* OR in size and CAS latency */
179 orr r1, r1, #CMMASK_REMAP /* set remap and led bits */
|
| /external/u-boot/arch/arm/cpu/arm920t/ep93xx/ |
| D | lowlevel_init.S | 248 orr r0, r0, #EP93XX_LED_RED_ON
261 orr r2, r2, r1
265 orr r2, r2, r1
269 orr r2, r2, r1
273 orr r2, r2, r1
277 orr r2, r2, r1
281 orr r2, r2, r1
339 orr r2, r11, #0x00008800
359 orr r2, r11, #0x00004600
376 orr r1, r1, #EP93XX_LED_GREEN_ON
[all …]
|
| /external/u-boot/arch/arm/mach-uniphier/arm32/ |
| D | debug_ll.S | 28 orr \rd, \rd, #(\muxval << (\pin * \mux_bits % 32))
45 orr r1, r1, #1
68 orr r1, r1, #SC_CLKCTRL_CEN_PERI
83 orr r1, r1, #1
109 orr r1, r1, #SC_CLKCTRL_CEN_PERI
124 orr r1, r1, #1
134 orr r1, r1, #SC_CLKCTRL_CEN_PERI
149 orr r1, r1, #1
158 orr r1, r1, #SC_CLKCTRL_CEN_PERI
|