1 /* SPDX-License-Identifier: GPL-2.0+ */ 2 /* 3 * LayerScape Internal Memory Map 4 * 5 * Copyright 2017-2019 NXP 6 * Copyright 2014 Freescale Semiconductor, Inc. 7 */ 8 9 #ifndef __ARCH_FSL_LSCH3_IMMAP_H_ 10 #define __ARCH_FSL_LSCH3_IMMAP_H_ 11 12 #define CONFIG_SYS_IMMR 0x01000000 13 #define CONFIG_SYS_FSL_DDR_ADDR (CONFIG_SYS_IMMR + 0x00080000) 14 #define CONFIG_SYS_FSL_DDR2_ADDR (CONFIG_SYS_IMMR + 0x00090000) 15 #define CONFIG_SYS_FSL_DDR3_ADDR 0x08210000 16 #define CONFIG_SYS_FSL_GUTS_ADDR (CONFIG_SYS_IMMR + 0x00E00000) 17 #define CONFIG_SYS_FSL_PMU_ADDR (CONFIG_SYS_IMMR + 0x00E30000) 18 #ifdef CONFIG_ARCH_LX2160A 19 #define CONFIG_SYS_FSL_RST_ADDR (CONFIG_SYS_IMMR + 0x00e88180) 20 #else 21 #define CONFIG_SYS_FSL_RST_ADDR (CONFIG_SYS_IMMR + 0x00E60000) 22 #endif 23 #define CONFIG_SYS_FSL_CH3_CLK_GRPA_ADDR (CONFIG_SYS_IMMR + 0x00300000) 24 #define CONFIG_SYS_FSL_CH3_CLK_GRPB_ADDR (CONFIG_SYS_IMMR + 0x00310000) 25 #define CONFIG_SYS_FSL_CH3_CLK_CTRL_ADDR (CONFIG_SYS_IMMR + 0x00370000) 26 #define SYS_FSL_QSPI_ADDR (CONFIG_SYS_IMMR + 0x010c0000) 27 #define CONFIG_SYS_FSL_ESDHC_ADDR (CONFIG_SYS_IMMR + 0x01140000) 28 #define FSL_ESDHC1_BASE_ADDR CONFIG_SYS_FSL_ESDHC_ADDR 29 #define FSL_ESDHC2_BASE_ADDR (CONFIG_SYS_IMMR + 0x01150000) 30 #ifndef CONFIG_NXP_LSCH3_2 31 #define CONFIG_SYS_IFC_ADDR (CONFIG_SYS_IMMR + 0x01240000) 32 #endif 33 #define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_IMMR + 0x011C0500) 34 #define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_IMMR + 0x011C0600) 35 #define SYS_FSL_LS2080A_LS2085A_TIMER_ADDR 0x023d0000 36 #define CONFIG_SYS_FSL_TIMER_ADDR 0x023e0000 37 #define CONFIG_SYS_FSL_PMU_CLTBENR (CONFIG_SYS_FSL_PMU_ADDR + \ 38 0x18A0) 39 #define FSL_PMU_PCTBENR_OFFSET (CONFIG_SYS_FSL_PMU_ADDR + 0x8A0) 40 #define FSL_LSCH3_SVR (CONFIG_SYS_FSL_GUTS_ADDR + 0xA4) 41 42 #define CONFIG_SYS_FSL_WRIOP1_ADDR (CONFIG_SYS_IMMR + 0x7B80000) 43 #define CONFIG_SYS_FSL_WRIOP1_MDIO1 (CONFIG_SYS_FSL_WRIOP1_ADDR + 0x16000) 44 #define CONFIG_SYS_FSL_WRIOP1_MDIO2 (CONFIG_SYS_FSL_WRIOP1_ADDR + 0x17000) 45 #define CONFIG_SYS_FSL_LSCH3_SERDES_ADDR (CONFIG_SYS_IMMR + 0xEA0000) 46 47 #define CONFIG_SYS_FSL_DCSR_DDR_ADDR 0x70012c000ULL 48 #define CONFIG_SYS_FSL_DCSR_DDR2_ADDR 0x70012d000ULL 49 #define CONFIG_SYS_FSL_DCSR_DDR3_ADDR 0x700132000ULL 50 #define CONFIG_SYS_FSL_DCSR_DDR4_ADDR 0x700133000ULL 51 52 #define I2C1_BASE_ADDR (CONFIG_SYS_IMMR + 0x01000000) 53 #define I2C2_BASE_ADDR (CONFIG_SYS_IMMR + 0x01010000) 54 #define I2C3_BASE_ADDR (CONFIG_SYS_IMMR + 0x01020000) 55 #define I2C4_BASE_ADDR (CONFIG_SYS_IMMR + 0x01030000) 56 #ifdef CONFIG_NXP_LSCH3_2 57 #define I2C5_BASE_ADDR (CONFIG_SYS_IMMR + 0x01040000) 58 #define I2C6_BASE_ADDR (CONFIG_SYS_IMMR + 0x01050000) 59 #define I2C7_BASE_ADDR (CONFIG_SYS_IMMR + 0x01060000) 60 #define I2C8_BASE_ADDR (CONFIG_SYS_IMMR + 0x01070000) 61 #endif 62 #define GPIO4_BASE_ADDR (CONFIG_SYS_IMMR + 0x01330000) 63 #define GPIO4_GPDIR_ADDR (GPIO4_BASE_ADDR + 0x0) 64 #define GPIO4_GPDAT_ADDR (GPIO4_BASE_ADDR + 0x8) 65 66 #define CONFIG_SYS_XHCI_USB1_ADDR (CONFIG_SYS_IMMR + 0x02100000) 67 #define CONFIG_SYS_XHCI_USB2_ADDR (CONFIG_SYS_IMMR + 0x02110000) 68 69 /* TZ Address Space Controller Definitions */ 70 #define TZASC1_BASE 0x01100000 /* as per CCSR map. */ 71 #define TZASC2_BASE 0x01110000 /* as per CCSR map. */ 72 #define TZASC3_BASE 0x01120000 /* as per CCSR map. */ 73 #define TZASC4_BASE 0x01130000 /* as per CCSR map. */ 74 #define TZASC_BUILD_CONFIG_REG(x) ((TZASC1_BASE + (x * 0x10000))) 75 #define TZASC_ACTION_REG(x) ((TZASC1_BASE + (x * 0x10000)) + 0x004) 76 #define TZASC_GATE_KEEPER(x) ((TZASC1_BASE + (x * 0x10000)) + 0x008) 77 #define TZASC_REGION_BASE_LOW_0(x) ((TZASC1_BASE + (x * 0x10000)) + 0x100) 78 #define TZASC_REGION_BASE_HIGH_0(x) ((TZASC1_BASE + (x * 0x10000)) + 0x104) 79 #define TZASC_REGION_TOP_LOW_0(x) ((TZASC1_BASE + (x * 0x10000)) + 0x108) 80 #define TZASC_REGION_TOP_HIGH_0(x) ((TZASC1_BASE + (x * 0x10000)) + 0x10C) 81 #define TZASC_REGION_ATTRIBUTES_0(x) ((TZASC1_BASE + (x * 0x10000)) + 0x110) 82 #define TZASC_REGION_ID_ACCESS_0(x) ((TZASC1_BASE + (x * 0x10000)) + 0x114) 83 84 /* EDMA */ 85 #define EDMA_BASE_ADDR (CONFIG_SYS_IMMR + 0x012c0000) 86 87 /* SATA */ 88 #define AHCI_BASE_ADDR1 (CONFIG_SYS_IMMR + 0x02200000) 89 #define AHCI_BASE_ADDR2 (CONFIG_SYS_IMMR + 0x02210000) 90 #define AHCI_BASE_ADDR3 (CONFIG_SYS_IMMR + 0x02220000) 91 #define AHCI_BASE_ADDR4 (CONFIG_SYS_IMMR + 0x02230000) 92 93 /* QDMA */ 94 #define QDMA_BASE_ADDR (CONFIG_SYS_IMMR + 0x07380000) 95 #define QMAN_CQSIDR_REG 0x20a80 96 97 /* DISPLAY */ 98 #define DISPLAY_BASE_ADDR (CONFIG_SYS_IMMR + 0x0e080000) 99 100 /* GPU */ 101 #define GPU_BASE_ADDR (CONFIG_SYS_IMMR + 0x0e0c0000) 102 103 /* SFP */ 104 #define CONFIG_SYS_SFP_ADDR (CONFIG_SYS_IMMR + 0x00e80200) 105 106 /* SEC */ 107 #define CONFIG_SYS_FSL_SEC_OFFSET 0x07000000ull 108 #define CONFIG_SYS_FSL_JR0_OFFSET 0x07010000ull 109 #define FSL_SEC_JR0_OFFSET CONFIG_SYS_FSL_JR0_OFFSET 110 #define FSL_SEC_JR1_OFFSET 0x07020000ull 111 #define FSL_SEC_JR2_OFFSET 0x07030000ull 112 #define FSL_SEC_JR3_OFFSET 0x07040000ull 113 #define CONFIG_SYS_FSL_SEC_ADDR \ 114 (CONFIG_SYS_IMMR + CONFIG_SYS_FSL_SEC_OFFSET) 115 #define CONFIG_SYS_FSL_JR0_ADDR \ 116 (CONFIG_SYS_IMMR + CONFIG_SYS_FSL_JR0_OFFSET) 117 #define FSL_SEC_JR0_BASE_ADDR (CONFIG_SYS_IMMR + FSL_SEC_JR0_OFFSET) 118 #define FSL_SEC_JR1_BASE_ADDR (CONFIG_SYS_IMMR + FSL_SEC_JR1_OFFSET) 119 #define FSL_SEC_JR2_BASE_ADDR (CONFIG_SYS_IMMR + FSL_SEC_JR2_OFFSET) 120 #define FSL_SEC_JR3_BASE_ADDR (CONFIG_SYS_IMMR + FSL_SEC_JR3_OFFSET) 121 122 #ifdef CONFIG_TFABOOT 123 #ifdef CONFIG_NXP_LSCH3_2 124 /* RCW_SRC field in Power-On Reset Control Register 1 */ 125 #define RCW_SRC_MASK 0x07800000 126 #define RCW_SRC_BIT 23 127 128 /* CFG_RCW_SRC[3:0] */ 129 #define RCW_SRC_TYPE_MASK 0x8 130 #define RCW_SRC_ADDR_OFFSET_8MB 0x800000 131 132 /* RCW SRC HARDCODED */ 133 #define RCW_SRC_HARDCODED_VAL 0x0 /* 0x00 - 0x07 */ 134 135 #define RCW_SRC_SDHC1_VAL 0x8 /* 0x8 */ 136 #define RCW_SRC_SDHC2_VAL 0x9 /* 0x9 */ 137 #define RCW_SRC_I2C1_VAL 0xa /* 0xa */ 138 #define RCW_SRC_RESERVED_UART_VAL 0xb /* 0xb */ 139 #define RCW_SRC_FLEXSPI_NAND2K_VAL 0xc /* 0xc */ 140 #define RCW_SRC_FLEXSPI_NAND4K_VAL 0xd /* 0xd */ 141 #define RCW_SRC_RESERVED_1_VAL 0xe /* 0xe */ 142 #define RCW_SRC_FLEXSPI_NOR_24B 0xf /* 0xf */ 143 #else 144 #define RCW_SRC_MASK (0xFF800000) 145 #define RCW_SRC_BIT 23 146 /* CFG_RCW_SRC[6:0] */ 147 #define RCW_SRC_TYPE_MASK (0x70) 148 149 /* RCW SRC HARDCODED */ 150 #define RCW_SRC_HARDCODED_VAL (0x10) /* 0x10 - 0x1f */ 151 /* Hardcoded will also have CFG_RCW_SRC[7] as 1. 0x90 - 0x9f */ 152 153 /* RCW SRC NOR */ 154 #define RCW_SRC_NOR_VAL (0x20) 155 #define NOR_TYPE_MASK (0x10) 156 #define NOR_16B_VAL (0x0) /* 0x20 - 0x2f */ 157 #define NOR_32B_VAL (0x10) /* 0x30 - 0x3f */ 158 159 /* RCW SRC Serial Flash 160 * 1. SERIAL NOR (QSPI) 161 * 2. OTHERS (SD/MMC, SPI, I2C1 162 */ 163 #define RCW_SRC_SERIAL_MASK (0x7F) 164 #define RCW_SRC_QSPI_VAL (0x62) /* 0x62 */ 165 #define RCW_SRC_SD_CARD_VAL (0x40) /* 0x40 */ 166 #define RCW_SRC_EMMC_VAL (0x41) /* 0x41 */ 167 #define RCW_SRC_I2C1_VAL (0x49) /* 0x49 */ 168 #endif 169 #endif 170 171 /* Security Monitor */ 172 #define CONFIG_SYS_SEC_MON_ADDR (CONFIG_SYS_IMMR + 0x00e90000) 173 174 /* MMU 500 */ 175 #define SMMU_SCR0 (SMMU_BASE + 0x0) 176 #define SMMU_SCR1 (SMMU_BASE + 0x4) 177 #define SMMU_SCR2 (SMMU_BASE + 0x8) 178 #define SMMU_SACR (SMMU_BASE + 0x10) 179 #define SMMU_IDR0 (SMMU_BASE + 0x20) 180 #define SMMU_IDR1 (SMMU_BASE + 0x24) 181 182 #define SMMU_NSCR0 (SMMU_BASE + 0x400) 183 #define SMMU_NSCR2 (SMMU_BASE + 0x408) 184 #define SMMU_NSACR (SMMU_BASE + 0x410) 185 186 #define SCR0_CLIENTPD_MASK 0x00000001 187 #define SCR0_USFCFG_MASK 0x00000400 188 189 190 /* PCIe */ 191 #define CONFIG_SYS_PCIE1_ADDR (CONFIG_SYS_IMMR + 0x2400000) 192 #define CONFIG_SYS_PCIE2_ADDR (CONFIG_SYS_IMMR + 0x2500000) 193 #define CONFIG_SYS_PCIE3_ADDR (CONFIG_SYS_IMMR + 0x2600000) 194 #define CONFIG_SYS_PCIE4_ADDR (CONFIG_SYS_IMMR + 0x2700000) 195 #ifdef CONFIG_ARCH_LX2160A 196 #define SYS_PCIE5_ADDR (CONFIG_SYS_IMMR + 0x2800000) 197 #define SYS_PCIE6_ADDR (CONFIG_SYS_IMMR + 0x2900000) 198 #endif 199 200 #ifdef CONFIG_ARCH_LX2160A 201 #define CONFIG_SYS_PCIE1_PHYS_ADDR 0x8000000000ULL 202 #define CONFIG_SYS_PCIE2_PHYS_ADDR 0x8800000000ULL 203 #define CONFIG_SYS_PCIE3_PHYS_ADDR 0x9000000000ULL 204 #define CONFIG_SYS_PCIE4_PHYS_ADDR 0x9800000000ULL 205 #define SYS_PCIE5_PHYS_ADDR 0xa000000000ULL 206 #define SYS_PCIE6_PHYS_ADDR 0xa800000000ULL 207 #elif CONFIG_ARCH_LS1088A 208 #define CONFIG_SYS_PCIE1_PHYS_ADDR 0x2000000000ULL 209 #define CONFIG_SYS_PCIE2_PHYS_ADDR 0x2800000000ULL 210 #define CONFIG_SYS_PCIE3_PHYS_ADDR 0x3000000000ULL 211 #elif CONFIG_ARCH_LS1028A 212 #define CONFIG_SYS_PCIE1_PHYS_ADDR 0x8000000000ULL 213 #define CONFIG_SYS_PCIE2_PHYS_ADDR 0x8800000000ULL 214 #define CONFIG_SYS_PCIE3_PHYS_ADDR 0x01f0000000ULL 215 /* this is used by integrated PCI on LS1028, includes ECAM and register space */ 216 #define CONFIG_SYS_PCIE3_PHYS_SIZE 0x0010000000ULL 217 #else 218 #define CONFIG_SYS_PCIE1_PHYS_ADDR 0x1000000000ULL 219 #define CONFIG_SYS_PCIE2_PHYS_ADDR 0x1200000000ULL 220 #define CONFIG_SYS_PCIE3_PHYS_ADDR 0x1400000000ULL 221 #define CONFIG_SYS_PCIE4_PHYS_ADDR 0x1600000000ULL 222 #endif 223 224 /* Device Configuration */ 225 #define DCFG_BASE 0x01e00000 226 #define DCFG_PORSR1 0x000 227 #define DCFG_PORSR1_RCW_SRC 0xff800000 228 #define DCFG_PORSR1_RCW_SRC_NOR 0x12f00000 229 #define DCFG_RCWSR13 0x130 230 #define DCFG_RCWSR13_DSPI (0 << 8) 231 #define DCFG_RCWSR15 0x138 232 #define DCFG_RCWSR15_IFCGRPABASE_QSPI 0x3 233 234 #define DCFG_DCSR_BASE 0X700100000ULL 235 #define DCFG_DCSR_PORCR1 0x000 236 237 /* Interrupt Sampling Control */ 238 #define ISC_BASE 0x01F70000 239 #define IRQCR_OFFSET 0x14 240 241 /* Supplemental Configuration */ 242 #define SCFG_BASE 0x01fc0000 243 #define SCFG_USB3PRM1CR 0x000 244 #define SCFG_USB3PRM1CR_INIT 0x27672b2a 245 #define SCFG_USB_TXVREFTUNE 0x9 246 #define SCFG_USB_SQRXTUNE_MASK 0x7 247 #define SCFG_QSPICLKCTLR 0x10 248 249 #define DCSR_BASE 0x700000000ULL 250 #define DCSR_USB_PHY1 0x4600000 251 #define DCSR_USB_PHY2 0x4610000 252 #define DCSR_USB_PHY_RX_OVRD_IN_HI 0x200C 253 #define USB_PHY_RX_EQ_VAL_1 0x0000 254 #define USB_PHY_RX_EQ_VAL_2 0x0080 255 #define USB_PHY_RX_EQ_VAL_3 0x0380 256 #define USB_PHY_RX_EQ_VAL_4 0x0b80 257 #define DCSR_USB_IOCR1 0x108004 258 #define DCSR_USB_PCSTXSWINGFULL 0x71 259 260 #define TP_ITYP_AV 0x00000001 /* Initiator available */ 261 #define TP_ITYP_TYPE(x) (((x) & 0x6) >> 1) /* Initiator Type */ 262 #define TP_ITYP_TYPE_ARM 0x0 263 #define TP_ITYP_TYPE_PPC 0x1 /* PowerPC */ 264 #define TP_ITYP_TYPE_OTHER 0x2 /* StarCore DSP */ 265 #define TP_ITYP_TYPE_HA 0x3 /* HW Accelerator */ 266 #define TP_ITYP_THDS(x) (((x) & 0x18) >> 3) /* # threads */ 267 #define TP_ITYP_VER(x) (((x) & 0xe0) >> 5) /* Initiator Version */ 268 #define TY_ITYP_VER_A7 0x1 269 #define TY_ITYP_VER_A53 0x2 270 #define TY_ITYP_VER_A57 0x3 271 #define TY_ITYP_VER_A72 0x4 272 273 #define TP_CLUSTER_EOC 0x80000000 /* end of clusters */ 274 #define TP_CLUSTER_INIT_MASK 0x0000003f /* initiator mask */ 275 #define TP_INIT_PER_CLUSTER 4 276 /* This is chassis generation 3 */ 277 #ifndef __ASSEMBLY__ 278 struct sys_info { 279 unsigned long freq_processor[CONFIG_MAX_CPUS]; 280 /* frequency of platform PLL */ 281 unsigned long freq_systembus; 282 unsigned long freq_ddrbus; 283 unsigned long freq_cga_m2; 284 #ifdef CONFIG_SYS_FSL_HAS_DP_DDR 285 unsigned long freq_ddrbus2; 286 #endif 287 unsigned long freq_localbus; 288 unsigned long freq_qe; 289 #ifdef CONFIG_SYS_DPAA_FMAN 290 unsigned long freq_fman[CONFIG_SYS_NUM_FMAN]; 291 #endif 292 #ifdef CONFIG_SYS_DPAA_QBMAN 293 unsigned long freq_qman; 294 #endif 295 #ifdef CONFIG_SYS_DPAA_PME 296 unsigned long freq_pme; 297 #endif 298 }; 299 300 /* Global Utilities Block */ 301 struct ccsr_gur { 302 u32 porsr1; /* POR status 1 */ 303 u32 porsr2; /* POR status 2 */ 304 u8 res_008[0x20-0x8]; 305 u32 gpporcr1; /* General-purpose POR configuration */ 306 u32 gpporcr2; /* General-purpose POR configuration 2 */ 307 u32 gpporcr3; 308 u32 gpporcr4; 309 u8 res_030[0x60-0x30]; 310 #define FSL_CHASSIS3_DCFG_FUSESR_VID_MASK 0x1F 311 #define FSL_CHASSIS3_DCFG_FUSESR_ALTVID_MASK 0x1F 312 #if defined(CONFIG_ARCH_LS1088A) 313 #define FSL_CHASSIS3_DCFG_FUSESR_VID_SHIFT 25 314 #define FSL_CHASSIS3_DCFG_FUSESR_ALTVID_SHIFT 20 315 #else 316 #define FSL_CHASSIS3_DCFG_FUSESR_VID_SHIFT 2 317 #define FSL_CHASSIS3_DCFG_FUSESR_ALTVID_SHIFT 7 318 #endif 319 u32 dcfg_fusesr; /* Fuse status register */ 320 u8 res_064[0x70-0x64]; 321 u32 devdisr; /* Device disable control 1 */ 322 u32 devdisr2; /* Device disable control 2 */ 323 u32 devdisr3; /* Device disable control 3 */ 324 u32 devdisr4; /* Device disable control 4 */ 325 u32 devdisr5; /* Device disable control 5 */ 326 u32 devdisr6; /* Device disable control 6 */ 327 u8 res_088[0x94-0x88]; 328 u32 coredisr; /* Device disable control 7 */ 329 #define FSL_CHASSIS3_DEVDISR2_DPMAC1 0x00000001 330 #define FSL_CHASSIS3_DEVDISR2_DPMAC2 0x00000002 331 #define FSL_CHASSIS3_DEVDISR2_DPMAC3 0x00000004 332 #define FSL_CHASSIS3_DEVDISR2_DPMAC4 0x00000008 333 #define FSL_CHASSIS3_DEVDISR2_DPMAC5 0x00000010 334 #define FSL_CHASSIS3_DEVDISR2_DPMAC6 0x00000020 335 #define FSL_CHASSIS3_DEVDISR2_DPMAC7 0x00000040 336 #define FSL_CHASSIS3_DEVDISR2_DPMAC8 0x00000080 337 #define FSL_CHASSIS3_DEVDISR2_DPMAC9 0x00000100 338 #define FSL_CHASSIS3_DEVDISR2_DPMAC10 0x00000200 339 #define FSL_CHASSIS3_DEVDISR2_DPMAC11 0x00000400 340 #define FSL_CHASSIS3_DEVDISR2_DPMAC12 0x00000800 341 #define FSL_CHASSIS3_DEVDISR2_DPMAC13 0x00001000 342 #define FSL_CHASSIS3_DEVDISR2_DPMAC14 0x00002000 343 #define FSL_CHASSIS3_DEVDISR2_DPMAC15 0x00004000 344 #define FSL_CHASSIS3_DEVDISR2_DPMAC16 0x00008000 345 #define FSL_CHASSIS3_DEVDISR2_DPMAC17 0x00010000 346 #define FSL_CHASSIS3_DEVDISR2_DPMAC18 0x00020000 347 #define FSL_CHASSIS3_DEVDISR2_DPMAC19 0x00040000 348 #define FSL_CHASSIS3_DEVDISR2_DPMAC20 0x00080000 349 #define FSL_CHASSIS3_DEVDISR2_DPMAC21 0x00100000 350 #define FSL_CHASSIS3_DEVDISR2_DPMAC22 0x00200000 351 #define FSL_CHASSIS3_DEVDISR2_DPMAC23 0x00400000 352 #define FSL_CHASSIS3_DEVDISR2_DPMAC24 0x00800000 353 u8 res_098[0xa0-0x98]; 354 u32 pvr; /* Processor version */ 355 u32 svr; /* System version */ 356 u8 res_0a8[0x100-0xa8]; 357 u32 rcwsr[30]; /* Reset control word status */ 358 359 #define FSL_CHASSIS3_RCWSR0_SYS_PLL_RAT_SHIFT 2 360 #define FSL_CHASSIS3_RCWSR0_SYS_PLL_RAT_MASK 0x1f 361 #define FSL_CHASSIS3_RCWSR0_MEM_PLL_RAT_SHIFT 10 362 #define FSL_CHASSIS3_RCWSR0_MEM_PLL_RAT_MASK 0x3f 363 #define FSL_CHASSIS3_RCWSR0_MEM2_PLL_RAT_SHIFT 18 364 #define FSL_CHASSIS3_RCWSR0_MEM2_PLL_RAT_MASK 0x3f 365 366 #if defined(CONFIG_ARCH_LS2080A) 367 #define FSL_CHASSIS3_RCWSR28_SRDS1_PRTCL_MASK 0x00FF0000 368 #define FSL_CHASSIS3_RCWSR28_SRDS1_PRTCL_SHIFT 16 369 #define FSL_CHASSIS3_RCWSR28_SRDS2_PRTCL_MASK 0xFF000000 370 #define FSL_CHASSIS3_RCWSR28_SRDS2_PRTCL_SHIFT 24 371 #define FSL_CHASSIS3_SRDS1_PRTCL_MASK FSL_CHASSIS3_RCWSR28_SRDS1_PRTCL_MASK 372 #define FSL_CHASSIS3_SRDS1_PRTCL_SHIFT FSL_CHASSIS3_RCWSR28_SRDS1_PRTCL_SHIFT 373 #define FSL_CHASSIS3_SRDS2_PRTCL_MASK FSL_CHASSIS3_RCWSR28_SRDS2_PRTCL_MASK 374 #define FSL_CHASSIS3_SRDS2_PRTCL_SHIFT FSL_CHASSIS3_RCWSR28_SRDS2_PRTCL_SHIFT 375 #define FSL_CHASSIS3_SRDS1_REGSR 29 376 #define FSL_CHASSIS3_SRDS2_REGSR 29 377 #elif defined(CONFIG_ARCH_LX2160A) 378 #define FSL_CHASSIS3_EC1_REGSR 27 379 #define FSL_CHASSIS3_EC2_REGSR 27 380 #define FSL_CHASSIS3_EC1_REGSR_PRTCL_MASK 0x00000003 381 #define FSL_CHASSIS3_EC1_REGSR_PRTCL_SHIFT 0 382 #define FSL_CHASSIS3_EC2_REGSR_PRTCL_MASK 0x00000007 383 #define FSL_CHASSIS3_EC2_REGSR_PRTCL_SHIFT 2 384 #define FSL_CHASSIS3_RCWSR28_SRDS1_PRTCL_MASK 0x001F0000 385 #define FSL_CHASSIS3_RCWSR28_SRDS1_PRTCL_SHIFT 16 386 #define FSL_CHASSIS3_RCWSR28_SRDS2_PRTCL_MASK 0x03E00000 387 #define FSL_CHASSIS3_RCWSR28_SRDS2_PRTCL_SHIFT 21 388 #define FSL_CHASSIS3_RCWSR28_SRDS3_PRTCL_MASK 0x7C000000 389 #define FSL_CHASSIS3_RCWSR28_SRDS3_PRTCL_SHIFT 26 390 #define FSL_CHASSIS3_SRDS1_PRTCL_MASK FSL_CHASSIS3_RCWSR28_SRDS1_PRTCL_MASK 391 #define FSL_CHASSIS3_SRDS1_PRTCL_SHIFT FSL_CHASSIS3_RCWSR28_SRDS1_PRTCL_SHIFT 392 #define FSL_CHASSIS3_SRDS2_PRTCL_MASK FSL_CHASSIS3_RCWSR28_SRDS2_PRTCL_MASK 393 #define FSL_CHASSIS3_SRDS2_PRTCL_SHIFT FSL_CHASSIS3_RCWSR28_SRDS2_PRTCL_SHIFT 394 #define FSL_CHASSIS3_SRDS3_PRTCL_MASK FSL_CHASSIS3_RCWSR28_SRDS3_PRTCL_MASK 395 #define FSL_CHASSIS3_SRDS3_PRTCL_SHIFT FSL_CHASSIS3_RCWSR28_SRDS3_PRTCL_SHIFT 396 #define FSL_CHASSIS3_SRDS1_REGSR 29 397 #define FSL_CHASSIS3_SRDS2_REGSR 29 398 #define FSL_CHASSIS3_SRDS3_REGSR 29 399 #define FSL_CHASSIS3_RCWSR12_REGSR 12 400 #define FSL_CHASSIS3_RCWSR13_REGSR 13 401 #define FSL_CHASSIS3_SDHC1_BASE_PMUX_MASK 0x07000000 402 #define FSL_CHASSIS3_SDHC1_BASE_PMUX_SHIFT 24 403 #define FSL_CHASSIS3_SDHC2_BASE_PMUX_MASK 0x00000038 404 #define FSL_CHASSIS3_SDHC2_BASE_PMUX_SHIFT 3 405 #define FSL_CHASSIS3_IIC5_PMUX_MASK 0x00000E00 406 #define FSL_CHASSIS3_IIC5_PMUX_SHIFT 9 407 #elif defined(CONFIG_ARCH_LS1088A) 408 #define FSL_CHASSIS3_EC1_REGSR 26 409 #define FSL_CHASSIS3_EC2_REGSR 26 410 #define FSL_CHASSIS3_RCWSR25_EC1_PRTCL_MASK 0x00000007 411 #define FSL_CHASSIS3_RCWSR25_EC1_PRTCL_SHIFT 0 412 #define FSL_CHASSIS3_RCWSR25_EC2_PRTCL_MASK 0x00000038 413 #define FSL_CHASSIS3_RCWSR25_EC2_PRTCL_SHIFT 3 414 #define FSL_CHASSIS3_RCWSR29_SRDS1_PRTCL_MASK 0xFFFF0000 415 #define FSL_CHASSIS3_RCWSR29_SRDS1_PRTCL_SHIFT 16 416 #define FSL_CHASSIS3_RCWSR30_SRDS2_PRTCL_MASK 0x0000FFFF 417 #define FSL_CHASSIS3_RCWSR30_SRDS2_PRTCL_SHIFT 0 418 #define FSL_CHASSIS3_SRDS1_PRTCL_MASK FSL_CHASSIS3_RCWSR29_SRDS1_PRTCL_MASK 419 #define FSL_CHASSIS3_SRDS1_PRTCL_SHIFT FSL_CHASSIS3_RCWSR29_SRDS1_PRTCL_SHIFT 420 #define FSL_CHASSIS3_SRDS2_PRTCL_MASK FSL_CHASSIS3_RCWSR30_SRDS2_PRTCL_MASK 421 #define FSL_CHASSIS3_SRDS2_PRTCL_SHIFT FSL_CHASSIS3_RCWSR30_SRDS2_PRTCL_SHIFT 422 #define FSL_CHASSIS3_SRDS1_REGSR 29 423 #define FSL_CHASSIS3_SRDS2_REGSR 30 424 #elif defined(CONFIG_ARCH_LS1028A) 425 #define FSL_CHASSIS3_RCWSR29_SRDS1_PRTCL_MASK 0xFFFF0000 426 #define FSL_CHASSIS3_RCWSR29_SRDS1_PRTCL_SHIFT 16 427 #define FSL_CHASSIS3_SRDS1_PRTCL_MASK FSL_CHASSIS3_RCWSR29_SRDS1_PRTCL_MASK 428 #define FSL_CHASSIS3_SRDS1_PRTCL_SHIFT FSL_CHASSIS3_RCWSR29_SRDS1_PRTCL_SHIFT 429 #define FSL_CHASSIS3_SRDS1_REGSR 29 430 #endif 431 #define RCW_SB_EN_REG_INDEX 9 432 #define RCW_SB_EN_MASK 0x00000400 433 434 u8 res_178[0x200-0x178]; 435 u32 scratchrw[16]; /* Scratch Read/Write */ 436 u8 res_240[0x300-0x240]; 437 u32 scratchw1r[4]; /* Scratch Read (Write once) */ 438 u8 res_310[0x400-0x310]; 439 u32 bootlocptrl; /* Boot location pointer low-order addr */ 440 u32 bootlocptrh; /* Boot location pointer high-order addr */ 441 u8 res_408[0x520-0x408]; 442 u32 usb1_amqr; 443 u32 usb2_amqr; 444 u8 res_528[0x530-0x528]; /* add more registers when needed */ 445 u32 sdmm1_amqr; 446 u32 sdmm2_amqr; 447 u8 res_538[0x550 - 0x538]; /* add more registers when needed */ 448 u32 sata1_amqr; 449 u32 sata2_amqr; 450 u32 sata3_amqr; 451 u32 sata4_amqr; 452 u8 res_560[0x570 - 0x560]; /* add more registers when needed */ 453 u32 misc1_amqr; 454 u8 res_574[0x590-0x574]; /* add more registers when needed */ 455 u32 spare1_amqr; 456 u32 spare2_amqr; 457 u32 spare3_amqr; 458 u8 res_59c[0x620 - 0x59c]; /* add more registers when needed */ 459 u32 gencr[7]; /* General Control Registers */ 460 u8 res_63c[0x640-0x63c]; /* add more registers when needed */ 461 u32 cgensr1; /* Core General Status Register */ 462 u8 res_644[0x660-0x644]; /* add more registers when needed */ 463 u32 cgencr1; /* Core General Control Register */ 464 u8 res_664[0x740-0x664]; /* add more registers when needed */ 465 u32 tp_ityp[64]; /* Topology Initiator Type Register */ 466 struct { 467 u32 upper; 468 u32 lower; 469 } tp_cluster[4]; /* Core cluster n Topology Register */ 470 u8 res_864[0x920-0x864]; /* add more registers when needed */ 471 u32 ioqoscr[8]; /*I/O Quality of Services Register */ 472 u32 uccr; 473 u8 res_944[0x960-0x944]; /* add more registers when needed */ 474 u32 ftmcr; 475 u8 res_964[0x990-0x964]; /* add more registers when needed */ 476 u32 coredisablesr; 477 u8 res_994[0xa00-0x994]; /* add more registers when needed */ 478 u32 sdbgcr; /*Secure Debug Confifuration Register */ 479 u8 res_a04[0xbf8-0xa04]; /* add more registers when needed */ 480 u32 ipbrr1; 481 u32 ipbrr2; 482 u8 res_858[0x1000-0xc00]; 483 }; 484 485 struct ccsr_clk_cluster_group { 486 struct { 487 u8 res_00[0x10]; 488 u32 csr; 489 u8 res_14[0x20-0x14]; 490 } hwncsr[3]; 491 u8 res_60[0x80-0x60]; 492 struct { 493 u32 gsr; 494 u8 res_84[0xa0-0x84]; 495 } pllngsr[3]; 496 u8 res_e0[0x100-0xe0]; 497 }; 498 499 struct ccsr_clk_ctrl { 500 struct { 501 u32 csr; /* core cluster n clock control status */ 502 u8 res_04[0x20-0x04]; 503 } clkcncsr[8]; 504 }; 505 506 struct ccsr_reset { 507 u32 rstcr; /* 0x000 */ 508 u32 rstcrsp; /* 0x004 */ 509 u8 res_008[0x10-0x08]; /* 0x008 */ 510 u32 rstrqmr1; /* 0x010 */ 511 u32 rstrqmr2; /* 0x014 */ 512 u32 rstrqsr1; /* 0x018 */ 513 u32 rstrqsr2; /* 0x01c */ 514 u32 rstrqwdtmrl; /* 0x020 */ 515 u32 rstrqwdtmru; /* 0x024 */ 516 u8 res_028[0x30-0x28]; /* 0x028 */ 517 u32 rstrqwdtsrl; /* 0x030 */ 518 u32 rstrqwdtsru; /* 0x034 */ 519 u8 res_038[0x60-0x38]; /* 0x038 */ 520 u32 brrl; /* 0x060 */ 521 u32 brru; /* 0x064 */ 522 u8 res_068[0x80-0x68]; /* 0x068 */ 523 u32 pirset; /* 0x080 */ 524 u32 pirclr; /* 0x084 */ 525 u8 res_088[0x90-0x88]; /* 0x088 */ 526 u32 brcorenbr; /* 0x090 */ 527 u8 res_094[0x100-0x94]; /* 0x094 */ 528 u32 rcw_reqr; /* 0x100 */ 529 u32 rcw_completion; /* 0x104 */ 530 u8 res_108[0x110-0x108]; /* 0x108 */ 531 u32 pbi_reqr; /* 0x110 */ 532 u32 pbi_completion; /* 0x114 */ 533 u8 res_118[0xa00-0x118]; /* 0x118 */ 534 u32 qmbm_warmrst; /* 0xa00 */ 535 u32 soc_warmrst; /* 0xa04 */ 536 u8 res_a08[0xbf8-0xa08]; /* 0xa08 */ 537 u32 ip_rev1; /* 0xbf8 */ 538 u32 ip_rev2; /* 0xbfc */ 539 }; 540 541 struct ccsr_serdes { 542 struct { 543 u32 rstctl; /* Reset Control Register */ 544 u32 pllcr0; /* PLL Control Register 0 */ 545 u32 pllcr1; /* PLL Control Register 1 */ 546 u32 pllcr2; /* PLL Control Register 2 */ 547 u32 pllcr3; /* PLL Control Register 3 */ 548 u32 pllcr4; /* PLL Control Register 4 */ 549 u32 pllcr5; /* PLL Control Register 5 */ 550 u8 res[0x20 - 0x1c]; 551 } bank[2]; 552 u8 res1[0x90 - 0x40]; 553 u32 srdstcalcr; /* TX Calibration Control */ 554 u32 srdstcalcr1; /* TX Calibration Control1 */ 555 u8 res2[0xa0 - 0x98]; 556 u32 srdsrcalcr; /* RX Calibration Control */ 557 u32 srdsrcalcr1; /* RX Calibration Control1 */ 558 u8 res3[0xb0 - 0xa8]; 559 u32 srdsgr0; /* General Register 0 */ 560 u8 res4[0x800 - 0xb4]; 561 struct serdes_lane { 562 u32 gcr0; /* General Control Register 0 */ 563 u32 gcr1; /* General Control Register 1 */ 564 u32 gcr2; /* General Control Register 2 */ 565 u32 ssc0; /* Speed Switch Control 0 */ 566 u32 rec0; /* Receive Equalization Control 0 */ 567 u32 rec1; /* Receive Equalization Control 1 */ 568 u32 tec0; /* Transmit Equalization Control 0 */ 569 u32 ssc1; /* Speed Switch Control 1 */ 570 u8 res1[0x840 - 0x820]; 571 } lane[8]; 572 u8 res5[0x19fc - 0xa00]; 573 }; 574 575 #endif /*__ASSEMBLY__*/ 576 #endif /* __ARCH_FSL_LSCH3_IMMAP_H_ */ 577