Searched refs:pclk_div (Results 1 – 12 of 12) sorted by relevance
82 u32 pclk_div; in rkclk_init() local102 pclk_div = APLL_HZ / CORE_PERI_HZ - 1; in rkclk_init()103 assert((pclk_div + 1) * CORE_PERI_HZ == APLL_HZ && pclk_div < 0xf); in rkclk_init()113 pclk_div << CORE_PERI_DIV_SHIFT); in rkclk_init()122 pclk_div = GPLL_HZ / BUS_PCLK_HZ - 1; in rkclk_init()123 assert((pclk_div + 1) * BUS_PCLK_HZ == GPLL_HZ && pclk_div <= 0x7); in rkclk_init()135 pclk_div << BUS_PCLK_DIV_SHIFT | in rkclk_init()149 pclk_div = ilog2(PERI_ACLK_HZ / PERI_PCLK_HZ); in rkclk_init()150 assert((1 << pclk_div) * PERI_PCLK_HZ == in rkclk_init()151 PERI_ACLK_HZ && pclk_div < 0x8); in rkclk_init()[all …]
83 u32 pclk_div; in rkclk_init() local103 pclk_div = APLL_HZ / CORE_PERI_HZ - 1; in rkclk_init()104 assert((pclk_div + 1) * CORE_PERI_HZ == APLL_HZ && pclk_div < 0xf); in rkclk_init()114 pclk_div << CORE_PERI_DIV_SHIFT); in rkclk_init()123 pclk_div = BUS_ACLK_HZ / BUS_PCLK_HZ - 1; in rkclk_init()124 assert((pclk_div + 1) * BUS_PCLK_HZ == BUS_ACLK_HZ && pclk_div <= 0x7); in rkclk_init()136 pclk_div << BUS_PCLK_DIV_SHIFT | in rkclk_init()150 pclk_div = ilog2(PERI_ACLK_HZ / PERI_PCLK_HZ); in rkclk_init()151 assert((1 << pclk_div) * PERI_PCLK_HZ == in rkclk_init()152 PERI_ACLK_HZ && pclk_div < 0x8); in rkclk_init()[all …]
144 u32 pclk_div; in rkclk_init() local164 pclk_div = APLL_HZ / CORE_PERI_HZ - 1; in rkclk_init()165 assert((pclk_div + 1) * CORE_PERI_HZ == APLL_HZ && pclk_div < 0xf); in rkclk_init()175 pclk_div << CORE_PERI_DIV_SHIFT); in rkclk_init()184 pclk_div = BUS_ACLK_HZ / BUS_PCLK_HZ - 1; in rkclk_init()185 assert((pclk_div + 1) * BUS_PCLK_HZ == BUS_ACLK_HZ && pclk_div <= 0x7); in rkclk_init()197 pclk_div << BUS_PCLK_DIV_SHIFT | in rkclk_init()211 pclk_div = ilog2(PERI_ACLK_HZ / PERI_PCLK_HZ); in rkclk_init()212 assert((1 << pclk_div) * PERI_PCLK_HZ == in rkclk_init()213 PERI_ACLK_HZ && pclk_div < 0x8); in rkclk_init()[all …]
375 u32 aclk_div, hclk_div, pclk_div, h2p_div; in rkclk_init() local410 pclk_div = ilog2(CPU_ACLK_HZ / CPU_PCLK_HZ); in rkclk_init()411 assert((1 << pclk_div) * CPU_PCLK_HZ == CPU_ACLK_HZ && pclk_div < 0x4); in rkclk_init()413 assert((1 << h2p_div) * CPU_H2P_HZ == CPU_HCLK_HZ && pclk_div < 0x3); in rkclk_init()420 pclk_div << CPU_PCLK_DIV_SHIFT | in rkclk_init()434 pclk_div = ilog2(PERI_ACLK_HZ / PERI_PCLK_HZ); in rkclk_init()435 assert((1 << pclk_div) * PERI_PCLK_HZ == in rkclk_init()436 PERI_ACLK_HZ && (pclk_div < 0x4)); in rkclk_init()443 pclk_div << PERI_PCLK_DIV_SHIFT | in rkclk_init()
1078 u32 pclk_div; in rkclk_init() local1103 pclk_div = PERIHP_ACLK_HZ / PERIHP_PCLK_HZ - 1; in rkclk_init()1104 assert((pclk_div + 1) * PERIHP_PCLK_HZ == in rkclk_init()1105 PERIHP_ACLK_HZ && (pclk_div < 0x7)); in rkclk_init()1110 pclk_div << PCLK_PERIHP_DIV_CON_SHIFT | in rkclk_init()1123 pclk_div = PERILP0_ACLK_HZ / PERILP0_PCLK_HZ - 1; in rkclk_init()1124 assert((pclk_div + 1) * PERILP0_PCLK_HZ == in rkclk_init()1125 PERILP0_ACLK_HZ && (pclk_div < 0x7)); in rkclk_init()1130 pclk_div << PCLK_PERILP0_DIV_CON_SHIFT | in rkclk_init()1140 pclk_div = PERILP1_HCLK_HZ / PERILP1_HCLK_HZ - 1; in rkclk_init()[all …]
425 u32 pclk_div; in rkclk_init() local453 pclk_div = PD_BUS_ACLK_HZ / PD_BUS_PCLK_HZ - 1; in rkclk_init()454 assert((pclk_div + 1) * PD_BUS_PCLK_HZ == in rkclk_init()455 PD_BUS_ACLK_HZ && pclk_div < 0x7); in rkclk_init()460 pclk_div << PD_BUS_PCLK_DIV_SHIFT | in rkclk_init()476 pclk_div = ilog2(PERI_ACLK_HZ / PERI_PCLK_HZ); in rkclk_init()477 assert((1 << pclk_div) * PERI_PCLK_HZ == in rkclk_init()478 PERI_ACLK_HZ && (pclk_div < 0x4)); in rkclk_init()484 pclk_div << PERI_PCLK_DIV_SHIFT | in rkclk_init()
283 u32 pclk_div; in rkclk_init() local294 pclk_div = PERIHP_ACLK_HZ / PERIHP_PCLK_HZ - 1; in rkclk_init()302 pclk_div << PCLK_PERIHP_DIV_CON_SHIFT | in rkclk_init()
34 .pclk_div = _pclk_div, \91 rate->pclk_div << CORE_DBG_DIV_SHIFT | in rk3308_armclk_set_clk()99 rate->pclk_div << CORE_DBG_DIV_SHIFT | in rk3308_armclk_set_clk()
46 .pclk_div = _pclk_div, \1137 rate->pclk_div << CORE_DBG_DIV_SHIFT | in px30_armclk_set_clk()1145 rate->pclk_div << CORE_DBG_DIV_SHIFT | in px30_armclk_set_clk()
75 const uint8_t pclk_div = in get_PCLK() local77 const ulong pclk_rate = get_HCLK() / pclk_div; in get_PCLK()
100 unsigned int pclk_div; member
115 unsigned int pclk_div; member