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Searched refs:per_pll (Results 1 – 7 of 7) sorted by relevance

/external/u-boot/arch/arm/mach-socfpga/
Dclock_manager_s10.c32 writel(val, &clock_manager_base->per_pll.bypass); in cm_write_bypass_perpll()
93 &clock_manager_base->per_pll.pllglob); in cm_basic_init()
94 writel(cfg->per_pll_fdbck, &clock_manager_base->per_pll.fdbck); in cm_basic_init()
95 writel(vcocalib, &clock_manager_base->per_pll.vcocalib); in cm_basic_init()
96 writel(cfg->per_pll_pllc0, &clock_manager_base->per_pll.pllc0); in cm_basic_init()
97 writel(cfg->per_pll_pllc1, &clock_manager_base->per_pll.pllc1); in cm_basic_init()
98 writel(cfg->per_pll_emacctl, &clock_manager_base->per_pll.emacctl); in cm_basic_init()
99 writel(cfg->per_pll_gpiodiv, &clock_manager_base->per_pll.gpiodiv); in cm_basic_init()
104 setbits_le32(&clock_manager_base->per_pll.pllglob, in cm_basic_init()
128 writel(0xff, &clock_manager_base->per_pll.cntr2clk); in cm_basic_init()
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Dclock_manager_gen5.c83 readl(&clock_manager_base->per_pll.en), in cm_basic_init()
84 &clock_manager_base->per_pll.en); in cm_basic_init()
98 writel(0, &clock_manager_base->per_pll.en); in cm_basic_init()
110 &clock_manager_base->per_pll.vco); in cm_basic_init()
123 &clock_manager_base->per_pll.src); in cm_basic_init()
129 readl(&clock_manager_base->per_pll.vco); in cm_basic_init()
138 writel(cfg->peri_vco_base, &clock_manager_base->per_pll.vco); in cm_basic_init()
164 writel(cfg->emac0clk, &clock_manager_base->per_pll.emac0clk); in cm_basic_init()
167 writel(cfg->emac1clk, &clock_manager_base->per_pll.emac1clk); in cm_basic_init()
172 writel(cfg->perqspiclk, &clock_manager_base->per_pll.perqspiclk); in cm_basic_init()
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Dclock_manager_arria10.c584 &clock_manager_base->per_pll.vco1); in cm_pll_ramp_periph()
589 per_cfg->vco1_numer, &clock_manager_base->per_pll.vco1); in cm_pll_ramp_periph()
644 writel(0, &clock_manager_base->per_pll.en); in cm_full_cfg()
650 &clock_manager_base->per_pll.bypasss); in cm_full_cfg()
665 &clock_manager_base->per_pll.vco0); in cm_full_cfg()
668 writel(CLKMGR_PERPLL_VCO1_RESET, &clock_manager_base->per_pll.vco1); in cm_full_cfg()
713 &clock_manager_base->per_pll.vco1); in cm_full_cfg()
717 &clock_manager_base->per_pll.vco1); in cm_full_cfg()
726 clrbits_le32(&clock_manager_base->per_pll.vco0, in cm_full_cfg()
738 writel((readl(&clock_manager_base->per_pll.vco0) & in cm_full_cfg()
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/external/u-boot/drivers/mmc/
Dsocfpga_dw_mmc.c59 clrbits_le32(&clock_manager_base->per_pll.en, in socfpga_dwmci_clksel()
70 setbits_le32(&clock_manager_base->per_pll.en, in socfpga_dwmci_clksel()
/external/u-boot/arch/arm/mach-socfpga/include/mach/
Dclock_manager_arria10.h88 struct socfpga_clock_manager_per_pll per_pll; member
Dclock_manager_s10.h139 struct socfpga_clock_manager_per_pll per_pll; member
Dclock_manager_gen5.h108 struct socfpga_clock_manager_per_pll per_pll; member