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Searched refs:phy_base (Results 1 – 25 of 35) sorted by relevance

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/external/u-boot/drivers/ram/rockchip/
Dsdram_phy_px30.c13 static void sdram_phy_dll_bypass_set(void __iomem *phy_base, u32 freq) in sdram_phy_dll_bypass_set() argument
19 setbits_le32(PHY_REG(phy_base, 0x13), 1 << 4); in sdram_phy_dll_bypass_set()
20 clrbits_le32(PHY_REG(phy_base, 0x14), 1 << 3); in sdram_phy_dll_bypass_set()
23 setbits_le32(PHY_REG(phy_base, j), 1 << 4); in sdram_phy_dll_bypass_set()
24 clrbits_le32(PHY_REG(phy_base, j + 0x1), 1 << 3); in sdram_phy_dll_bypass_set()
29 setbits_le32(PHY_REG(phy_base, 0xa4), 0x1f); in sdram_phy_dll_bypass_set()
31 clrbits_le32(PHY_REG(phy_base, 0xa4), 0x1f); in sdram_phy_dll_bypass_set()
46 writel(tmp, PHY_REG(phy_base, j)); in sdram_phy_dll_bypass_set()
50 static void sdram_phy_set_ds_odt(void __iomem *phy_base, in sdram_phy_set_ds_odt() argument
71 writel(cmd_drv, PHY_REG(phy_base, 0x11)); in sdram_phy_set_ds_odt()
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Dsdram_rk3328.c120 void __iomem *phy_base = dram->phy; in rkclk_configure_ddr() local
123 clrbits_le32(PHY_REG(phy_base, 0xef), 1 << 7); in rkclk_configure_ddr()
259 void __iomem *phy_base = dram->phy; in rx_deskew_switch_adjust() local
262 gate_val = MAX(readl(PHY_REG(phy_base, 0xfb + i)), gate_val); in rx_deskew_switch_adjust()
266 clrsetbits_le32(PHY_REG(phy_base, 0x6e), 0xc, (deskew_val & 0x3) << 2); in rx_deskew_switch_adjust()
267 clrsetbits_le32(PHY_REG(phy_base, 0x6f), 0x7 << 4, in rx_deskew_switch_adjust()
273 void __iomem *phy_base = dram->phy; in tx_deskew_switch_adjust() local
275 clrsetbits_le32(PHY_REG(phy_base, 0x6e), 0x3, 1); in tx_deskew_switch_adjust()
Dsdram_px30.c308 void __iomem *phy_base = dram->phy; in check_rd_gate() local
315 bw = (readl(PHY_REG(phy_base, 0x0)) >> 4) & 0xf; in check_rd_gate()
330 gate[i] = readl(PHY_REG(phy_base, 0xfb + i)); in check_rd_gate()
426 void __iomem *phy_base = dram->phy; in enable_low_power() local
453 setbits_le32(PHY_REG(phy_base, 7), 1 << 7); in enable_low_power()
/external/u-boot/arch/arm/mach-uniphier/dram/
Dumc-pxs2.c59 static void ddrphy_fifo_reset(void __iomem *phy_base) in ddrphy_fifo_reset() argument
63 tmp = readl(phy_base + MPHY_PGCR0); in ddrphy_fifo_reset()
65 writel(tmp, phy_base + MPHY_PGCR0); in ddrphy_fifo_reset()
70 writel(tmp, phy_base + MPHY_PGCR0); in ddrphy_fifo_reset()
75 static void ddrphy_vt_ctrl(void __iomem *phy_base, int enable) in ddrphy_vt_ctrl() argument
79 tmp = readl(phy_base + MPHY_PGCR1); in ddrphy_vt_ctrl()
86 writel(tmp, phy_base + MPHY_PGCR1); in ddrphy_vt_ctrl()
89 while (!(readl(phy_base + MPHY_PGSR1) & MPHY_PGSR1_VTSTOP)) in ddrphy_vt_ctrl()
94 static void ddrphy_dqs_delay_fixup(void __iomem *phy_base, int nr_dx, int step) in ddrphy_dqs_delay_fixup() argument
98 void __iomem *dx_base = phy_base + MPHY_DX_BASE; in ddrphy_dqs_delay_fixup()
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Dddrphy-ld4.c31 int uniphier_ld4_ddrphy_init(void __iomem *phy_base, int freq, bool ddr3plus) in uniphier_ld4_ddrphy_init() argument
48 writel(0x0300c473, phy_base + PHY_PGCR1); in uniphier_ld4_ddrphy_init()
49 writel(ddrphy_ptr0[freq_e], phy_base + PHY_PTR0); in uniphier_ld4_ddrphy_init()
50 writel(ddrphy_ptr1[freq_e], phy_base + PHY_PTR1); in uniphier_ld4_ddrphy_init()
51 writel(0x00083DEF, phy_base + PHY_PTR2); in uniphier_ld4_ddrphy_init()
52 writel(ddrphy_ptr3[freq_e], phy_base + PHY_PTR3); in uniphier_ld4_ddrphy_init()
53 writel(ddrphy_ptr4[freq_e], phy_base + PHY_PTR4); in uniphier_ld4_ddrphy_init()
54 writel(0xF004001A, phy_base + PHY_DSGCR); in uniphier_ld4_ddrphy_init()
57 tmp = readl(phy_base + PHY_DXCCR); in uniphier_ld4_ddrphy_init()
60 writel(tmp, phy_base + PHY_DXCCR); in uniphier_ld4_ddrphy_init()
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Dcmd_ddrmphy.c73 void __iomem *phy_base, *dx_base; in dump_loop() local
77 phy_base = ioremap(param->phy[phy].base, SZ_4K); in dump_loop()
78 dx_base = phy_base + MPHY_DX_BASE; in dump_loop()
87 iounmap(phy_base); in dump_loop()
93 void __iomem *phy_base, *zq_base; in zq_dump() local
101 phy_base = ioremap(param->phy[phy].base, SZ_4K); in zq_dump()
102 zq_base = phy_base + MPHY_ZQ_BASE; in zq_dump()
123 iounmap(phy_base); in zq_dump()
229 { int ofst = MPHY_ ## x; void __iomem *reg = phy_base + ofst; \
236 void __iomem *reg = phy_base + ofst; \
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Dddrphy-training.c21 void ddrphy_prepare_training(void __iomem *phy_base, int rank) in ddrphy_prepare_training() argument
23 void __iomem *dx_base = phy_base + PHY_DX_BASE; in ddrphy_prepare_training()
37 tmp = readl(phy_base + PHY_DTCR); in ddrphy_prepare_training()
46 writel(tmp, phy_base + PHY_DTCR); in ddrphy_prepare_training()
107 int ddrphy_training(void __iomem *phy_base) in ddrphy_training() argument
123 writel(init_flag, phy_base + PHY_PIR); in ddrphy_training()
131 pgsr0 = readl(phy_base + PHY_PGSR0); in ddrphy_training()
Dcmd_ddrphy.c88 void __iomem *phy_base, *dx_base; in dump_loop() local
92 phy_base = ioremap(param->phy[phy].base, SZ_4K); in dump_loop()
93 dx_base = phy_base + PHY_DX_BASE; in dump_loop()
102 iounmap(phy_base); in dump_loop()
203 { int ofst = PHY_ ## x; void __iomem *reg = phy_base + ofst; \
211 void __iomem *reg = phy_base + ofst; \
218 void __iomem *phy_base; in reg_dump() local
224 phy_base = ioremap(param->phy[phy].base, SZ_4K); in reg_dump()
227 phy, ptr_to_uint(phy_base)); in reg_dump()
260 iounmap(phy_base); in reg_dump()
Dddrphy-init.h12 int uniphier_ld4_ddrphy_init(void __iomem *phy_base, int freq, bool ddr3plus);
13 void ddrphy_prepare_training(void __iomem *phy_base, int rank);
14 int ddrphy_training(void __iomem *phy_base);
Dumc-pro4.c134 void __iomem *phy_base = dc_base + 0x00001000; in umc_ch_init() local
146 ret = uniphier_ld4_ddrphy_init(phy_base, freq, ddr3plus); in umc_ch_init()
150 ddrphy_prepare_training(phy_base, phy); in umc_ch_init()
151 ret = ddrphy_training(phy_base); in umc_ch_init()
155 phy_base += 0x00001000; in umc_ch_init()
Dumc-ld4.c147 void __iomem *phy_base = dc_base + 0x00001000; in umc_ch_init() local
156 ret = uniphier_ld4_ddrphy_init(phy_base, freq, ddr3plus); in umc_ch_init()
160 ddrphy_prepare_training(phy_base, umc_get_rank(ch)); in umc_ch_init()
161 ret = ddrphy_training(phy_base); in umc_ch_init()
Dumc-sld8.c150 void __iomem *phy_base = dc_base + 0x00001000; in umc_ch_init() local
159 ret = uniphier_ld4_ddrphy_init(phy_base, freq, ddr3plus); in umc_ch_init()
163 ddrphy_prepare_training(phy_base, umc_get_rank(ch)); in umc_ch_init()
164 ret = ddrphy_training(phy_base); in umc_ch_init()
/external/u-boot/arch/arm/include/asm/arch-rockchip/
Dsdram_phy_px30.h55 void phy_soft_reset(void __iomem *phy_base);
56 void phy_dram_set_bw(void __iomem *phy_base, u32 bw);
57 void phy_cfg(void __iomem *phy_base,
60 int phy_data_training(void __iomem *phy_base, u32 cs, u32 dramtype);
/external/u-boot/drivers/usb/host/
Dxhci-exynos5.c37 fdt_addr_t phy_base; member
80 plat->phy_base = fdtdec_get_addr(blob, node, "reg"); in xhci_usb_ofdata_to_platdata()
81 if (plat->phy_base == FDT_ADDR_T_NONE) { in xhci_usb_ofdata_to_platdata()
212 ctx->usb3_phy = (struct exynos_usb3_phy *)plat->phy_base; in xhci_usb_probe()
Dehci-exynos.c30 fdt_addr_t phy_base; member
71 plat->phy_base = fdtdec_get_addr(blob, node, "reg"); in ehci_usb_ofdata_to_platdata()
72 if (plat->phy_base == FDT_ADDR_T_NONE) { in ehci_usb_ofdata_to_platdata()
220 ctx->usb = (struct exynos_usb_phy *)plat->phy_base; in ehci_usb_probe()
/external/u-boot/drivers/phy/
Domap-usb2-phy.c35 void *phy_base; member
139 val = readl(priv->phy_base + USB2PHY_ANA_CONFIG1); in omap_usb2_phy_init()
141 writel(val, priv->phy_base + USB2PHY_ANA_CONFIG1); in omap_usb2_phy_init()
186 priv->phy_base = (void *)base; in omap_usb2_phy_probe()
/external/cpuinfo/test/dmesg/
Dnexus6.log450 [ 0.477009] mdss_dsi_retrieve_ctrl_resources: ctrl_base=cd73a800 ctrl_size=200 phy_base=cd73cb00…
471 [ 0.521605] mdss_dsi_retrieve_ctrl_resources: ctrl_base=cd752e00 ctrl_size=200 phy_base=cd754100…
Dnexus6p.log580 [ 0.872829] mdss_dsi_retrieve_ctrl_resources: ctrl_base=ffffff800137c000 ctrl_size=470 phy_base=…
598 [ 0.905854] mdss_dsi_retrieve_ctrl_resources: ctrl_base=ffffff8001432000 ctrl_size=470 phy_base=…
Doppo-a37.log330 …s_dsi_retrieve_ctrl_resources: ctrl_base=ffffff80001c2000 ctrl_size=25c phy_base=ffffff80001f2500 …
Dmoto-g-gen2.log319 [ 0.715656,0] mdss_dsi_retrieve_ctrl_resources: ctrl_base=e69fe800 ctrl_size=1f8 phy_base=e6a52b…
Dmoto-g-gen3.log90 [ 0.424668,0] mdss_dsi_retrieve_ctrl_resources: ctrl_base=c60fc000 ctrl_size=25c phy_base=c60fe5…
Dmoto-g-gen4.log4 [ 0.718799,0] mdss_dsi_retrieve_ctrl_resources: ctrl_base=c5186000 ctrl_size=25c phy_base=c518c5…
Dlg-k10-eu.log687 …309] mdss_dsi_retrieve_ctrl_resources: ctrl_base=c32d0000 ctrl_size=25c phy_base=c32d2500 phy_size…
Dpixel-xl.log297 …s_dsi_retrieve_ctrl_resources: ctrl_base=ffffff8001b96000 ctrl_size=400 phy_base=ffffff8001b98400 …
322 …s_dsi_retrieve_ctrl_resources: ctrl_base=ffffff8001b9c000 ctrl_size=400 phy_base=ffffff8001b9e400 …
Dmoto-g-gen5.log59 [ 0.578304,2] mdss_dsi_retrieve_ctrl_resources: ctrl_base=e69fe000 ctrl_size=300 phy_base=e6b024…

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