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Searched refs:physreg (Results 1 – 25 of 27) sorted by relevance

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/external/swiftshader/third_party/llvm-7.0/llvm/test/CodeGen/AArch64/
Dregcoal-physreg.mir81 ; Cannot coalesce when there are reads of the physreg.
96 ; Cannot coalesce physreg because we have reads on other CFG paths (we
119 ; We can coalesce copies from physreg to vreg across multiple blocks.
/external/swiftshader/third_party/llvm-7.0/llvm/test/CodeGen/MIR/X86/
Dsubreg-on-physreg.mir2 # This test ensures that an error is reported for subreg index on a physreg.
/external/swiftshader/third_party/llvm-7.0/llvm/test/CodeGen/X86/
D2011-06-14-PreschedRegalias.ll3 ; Test interference between physreg aliases during preRAsched.
Dphys_subreg_coalesce-3.ll4 ; This requires physreg joining, %13 is live everywhere:
Dfold-call-oper.ll3 ; PR18396: Assertion: MO->isDead "Cannot fold physreg def".
/external/llvm/test/CodeGen/X86/
D2011-06-14-PreschedRegalias.ll3 ; Test interference between physreg aliases during preRAsched.
Dphys_subreg_coalesce-3.ll4 ; This requires physreg joining, %vreg13 is live everywhere:
Dfold-call-oper.ll3 ; PR18396: Assertion: MO->isDead "Cannot fold physreg def".
/external/llvm/test/CodeGen/PowerPC/
D2010-10-11-Fast-Varargs.ll6 ; RegAllocFast requires that each physreg only be used once. The varargs
D2012-11-16-mischedcall.ll3 ; PR14315: misched should not move the physreg copy of %t below the calls.
/external/swiftshader/third_party/llvm-7.0/llvm/test/CodeGen/PowerPC/
D2010-10-11-Fast-Varargs.ll6 ; RegAllocFast requires that each physreg only be used once. The varargs
D2012-11-16-mischedcall.ll3 ; PR14315: misched should not move the physreg copy of %t below the calls.
/external/swiftshader/third_party/llvm-7.0/llvm/test/CodeGen/ARM/
Dregpair_hint_phys.ll3 ; physreg.
Dscavenging.mir4 # Make sure we are not spilling/using a physreg used in the very last
D2010-05-17-FastAllocCrash.ll4 ; This test case would accidentally use the same physreg for two virtregs
Dcmpxchg-O0.ll113 ; for a physreg with RC==GPRPairRegClass.
/external/llvm/test/CodeGen/ARM/
Dregpair_hint_phys.ll3 ; physreg.
D2010-05-17-FastAllocCrash.ll4 ; This test case would accidentally use the same physreg for two virtregs
Dcmpxchg-O0.ll105 ; for a physreg with RC==GPRPairRegClass.
/external/llvm/test/CodeGen/Generic/
D2006-07-03-schedulers.ll7 ; targets that use physreg defs.
/external/swiftshader/third_party/llvm-7.0/llvm/test/CodeGen/Generic/
D2006-07-03-schedulers.ll7 ; targets that use physreg defs.
/external/mesa3d/src/gallium/drivers/lima/ir/gp/
Dscheduler.c1029 int physreg = ffsll(available) - 1; in try_spill_node() local
1031 ctx->live_physregs |= (1ull << physreg); in try_spill_node()
1034 store->index = physreg / 4; in try_spill_node()
1035 store->component = physreg % 4; in try_spill_node()
1052 &ctx->physreg_reads[physreg], reg_link) { in try_spill_node()
/external/swiftshader/third_party/llvm-7.0/llvm/test/CodeGen/AArch64/GlobalISel/
Dselect-binop.mir534 # there is only MADDWrrr, and we have to use the WZR physreg.
/external/swiftshader/third_party/llvm-7.0/llvm/test/CodeGen/AMDGPU/
Dload-lo16.ll33 ; Show that we get reasonable regalloc without physreg constraints.
Dload-hi16.ll35 ; Show that we get reasonable regalloc without physreg constraints.

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