Home
last modified time | relevance | path

Searched refs:pll_base (Results 1 – 9 of 9) sorted by relevance

/external/u-boot/arch/arm/mach-davinci/
Dcpu.c40 unsigned int pll_base; in clk_get() local
48 pll_base = (unsigned int)davinci_pllc1_regs; in clk_get()
50 pll_base = (unsigned int)davinci_pllc0_regs; in clk_get()
58 pre_div = (readl(pll_base + PLLC_PREDIV) & in clk_get()
60 pllm = readl(pll_base + PLLC_PLLM) + 1; in clk_get()
68 post_div = (readl(pll_base + PLLC_POSTDIV) & in clk_get()
76 pll_out /= (readl(pll_base + sysdiv[id - 1]) & in clk_get()
/external/u-boot/arch/arm/mach-imx/imx8m/
Dclock_imx8mm.c68 void *pll_base; in fracpll_configure() local
89 pll_base = &ana_pll->dram_pll_gnrl_ctl; in fracpll_configure()
92 pll_base = &ana_pll->video_pll1_gnrl_ctl; in fracpll_configure()
98 tmp = readl(pll_base); in fracpll_configure()
100 writel(tmp, pll_base); in fracpll_configure()
104 writel(tmp, pll_base); in fracpll_configure()
108 writel(div_val, pll_base + 4); in fracpll_configure()
109 writel(rate->kdiv << KDIV_SHIFT, pll_base + 8); in fracpll_configure()
115 writel(tmp, pll_base); in fracpll_configure()
118 while (!(readl(pll_base) & LOCK_STATUS)) in fracpll_configure()
[all …]
/external/u-boot/arch/arm/mach-tegra/
Dcpu.c179 if (readl(&pll->pll_base) & PLL_ENABLE_MASK) { in pllx_set_rate()
189 writel(reg, &pll->pll_base); in pllx_set_rate()
207 reg = readl(&pll->pll_base); in pllx_set_rate()
209 writel(reg, &pll->pll_base); in pllx_set_rate()
220 reg = readl(&pll->pll_base); in pllx_set_rate()
222 writel(reg, &pll->pll_base); in pllx_set_rate()
Dclock.c102 data = readl(&pll->pll_base); in clock_ll_read_pll()
154 writel(data, &pll->pll_base); in clock_start_pll()
157 writel(data, &simple_pll->pll_base); in clock_start_pll()
551 base = readl(&pll->pll_base); in clock_get_rate()
598 base_reg = readl(&pll->pll_base); in clock_set_rate()
617 if (base_reg != readl(&pll->pll_base)) in clock_set_rate()
625 writel(base_reg, &pll->pll_base); in clock_set_rate()
635 writel(base_reg, &pll->pll_base); in clock_set_rate()
639 writel(base_reg, &pll->pll_base); in clock_set_rate()
677 u32 reg = readl(&pll->pll_base); in clock_verify()
/external/arm-trusted-firmware/plat/rockchip/px30/drivers/pmu/
Dpmu.c855 static inline void pm_pll_wait_lock(uint32_t pll_base, uint32_t pll_id) in pm_pll_wait_lock() argument
860 if (mmio_read_32(pll_base + PLL_CON(1)) & in pm_pll_wait_lock()
870 static inline void pll_pwr_ctr(uint32_t pll_base, uint32_t pll_id, uint32_t pd) in pll_pwr_ctr() argument
872 mmio_write_32(pll_base + PLL_CON(1), in pll_pwr_ctr()
875 mmio_write_32(pll_base + PLL_CON(1), in pll_pwr_ctr()
878 mmio_write_32(pll_base + PLL_CON(1), in pll_pwr_ctr()
896 uint32_t pll_base; in pll_suspend() local
899 pll_base = CRU_BASE + CRU_PLL_CONS(pll_id, 0); in pll_suspend()
901 pll_base = PMUCRU_BASE + CRU_PLL_CONS(0, 0); in pll_suspend()
906 mmio_read_32(pll_base + PLL_CON(i)); in pll_suspend()
[all …]
/external/u-boot/arch/arm/mach-tegra/tegra20/
Dwarmboot_avp.c188 writel(pllx_base.word, &clkrst->crc_pll_simple[SIMPLE_PLLX].pll_base); in wb_start()
191 writel(pllx_base.word, &clkrst->crc_pll_simple[SIMPLE_PLLX].pll_base); in wb_start()
193 writel(pllx_base.word, &clkrst->crc_pll_simple[SIMPLE_PLLX].pll_base); in wb_start()
/external/u-boot/arch/arm/include/asm/arch-tegra/
Dclk_rst.h12 uint pll_base; /* the control register */ member
20 uint pll_base; /* the control register */ member
/external/u-boot/arch/arm/mach-tegra/tegra114/
Dcpu.c61 reg = readl(&clkrst->crc_pll_simple[SIMPLE_PLLX].pll_base); in enable_cpu_clocks()
/external/u-boot/arch/arm/mach-tegra/tegra124/
Dcpu.c54 reg = readl(&clkrst->crc_pll_simple[SIMPLE_PLLX].pll_base); in enable_cpu_clocks()