Searched refs:pll_cfg (Results 1 – 2 of 2) sorted by relevance
109 const struct ar934x_pll_config *pll_cfg; in ar934x_pll_init() local142 pll_cfg = &ar934x_clock_config[i].cpu_pll; in ar934x_pll_init()143 pll_nint = pll_cfg->nint[xtal_40]; in ar934x_pll_init()144 pll_refdiv = pll_cfg->refdiv; in ar934x_pll_init()148 (pll_cfg->range << AR934X_PLL_CPU_CONFIG_RANGE_SHIFT) | in ar934x_pll_init()149 (pll_cfg->outdiv << AR934X_PLL_CPU_CONFIG_OUTDIV_SHIFT); in ar934x_pll_init()151 pll_cfg = &ar934x_clock_config[i].ddr_pll; in ar934x_pll_init()152 pll_nint = pll_cfg->nint[xtal_40]; in ar934x_pll_init()153 pll_refdiv = pll_cfg->refdiv; in ar934x_pll_init()157 (pll_cfg->range << AR934X_PLL_DDR_CONFIG_RANGE_SHIFT) | in ar934x_pll_init()[all …]
240 const struct hsdk_pll_cfg *pll_cfg; member251 .pll_cfg = asdt_pll_cfg,256 .pll_cfg = asdt_pll_cfg,261 .pll_cfg = hdmi_pll_cfg,406 const struct hsdk_pll_cfg *pll_cfg = clk->pll_devdata->pll_cfg; in hsdk_pll_round_rate() local408 if (pll_cfg[0].rate == 0) in hsdk_pll_round_rate()411 best_rate = pll_cfg[0].rate; in hsdk_pll_round_rate()413 for (i = 1; pll_cfg[i].rate != 0; i++) { in hsdk_pll_round_rate()414 if (abs(rate - pll_cfg[i].rate) < abs(rate - best_rate)) in hsdk_pll_round_rate()415 best_rate = pll_cfg[i].rate; in hsdk_pll_round_rate()[all …]