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Searched refs:pll_config (Results 1 – 7 of 7) sorted by relevance

/external/u-boot/drivers/clk/renesas/
Dclk-rcar-gen3.c161 const struct rcar_gen3_cpg_pll_config *pll_config = in gen3_clk_get_rate64() local
205 rate = gen3_clk_get_rate64(&parent) / pll_config->extal_div; in gen3_clk_get_rate64()
208 core->parent, pll_config->extal_div, rate); in gen3_clk_get_rate64()
220 rate = gen3_clk_get_rate64(&parent) * pll_config->pll1_mult; in gen3_clk_get_rate64()
221 rate /= pll_config->pll1_div; in gen3_clk_get_rate64()
224 core->parent, pll_config->pll1_mult, in gen3_clk_get_rate64()
225 pll_config->pll1_div, rate); in gen3_clk_get_rate64()
237 rate = gen3_clk_get_rate64(&parent) * pll_config->pll3_mult; in gen3_clk_get_rate64()
238 rate /= pll_config->pll3_div; in gen3_clk_get_rate64()
241 core->parent, pll_config->pll3_mult, in gen3_clk_get_rate64()
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Dclk-rcar-gen2.c80 const struct rcar_gen2_cpg_pll_config *pll_config = in gen2_clk_get_rate() local
138 rate = gen2_clk_get_rate(&parent) / pll_config->extal_div; in gen2_clk_get_rate()
141 core->parent, pll_config->extal_div, rate); in gen2_clk_get_rate()
151 mult = pll_config->pll0_mult; in gen2_clk_get_rate()
163 rate = (gen2_clk_get_rate(&parent) * pll_config->pll1_mult) / 2; in gen2_clk_get_rate()
166 core->parent, pll_config->pll1_mult, rate); in gen2_clk_get_rate()
170 rate = gen2_clk_get_rate(&parent) * pll_config->pll3_mult; in gen2_clk_get_rate()
173 core->parent, pll_config->pll3_mult, rate); in gen2_clk_get_rate()
/external/u-boot/drivers/video/
Dssd2828.c277 static u32 decode_pll_config(u32 pll_config, u32 reference_freq_khz) in decode_pll_config() argument
279 u32 mul_factor = pll_config & 0xFF; in decode_pll_config()
280 u32 div_factor = (pll_config >> 8) & 0x1F; in decode_pll_config()
342 u32 lp_div, pll_freq_kbps, reference_freq_khz, pll_config; in ssd2828_init() local
404 pll_config = construct_pll_config( in ssd2828_init()
407 write_hw_register(cfg, SSD2828_PLCR, pll_config); in ssd2828_init()
409 pll_freq_kbps = decode_pll_config(pll_config, reference_freq_khz); in ssd2828_init()
/external/u-boot/arch/arm/mach-omap2/am33xx/
Dclock_ti814x.c223 static void pll_config(u32 base, u32 n, u32 m, u32 m2, in pll_config() function
308 pll_config(MPU_PLL_BASE, MPU_N, MPU_M, MPU_M2, MPU_CLKCTRL, 0); in mpu_pll_config()
323 pll_config(L3_PLL_BASE, L3_N, L3_M, L3_M2, L3_CLKCTRL, 1); in l3_pll_config()
328 pll_config(DDR_PLL_BASE, DDR_N, DDR_M, DDR_M2, DDR_CLKCTRL, 1); in ddr_pll_config()
/external/u-boot/arch/arm/mach-socfpga/
Dqts-filter.sh117 ${in_bsp_dir}/generated/pll_config.h |
/external/u-boot/doc/
DREADME.socfpga131 pll_config.h
143 -rw-r--r-- 1 sarnold sarnold 3190 Mar 21 18:11 pll_config.h
/external/u-boot/drivers/clk/
Dclk_stm32mp1.c1395 static int pll_config(struct stm32mp1_clk_priv *priv, int pll_id, in pll_config() function
1517 pll_config(priv, pll_id, pllcfg, fracv); in pll_set_rate()
1777 pll_config(priv, i, pllcfg[i], fracv); in stm32mp1_clktree()