Searched refs:pll_out (Results 1 – 7 of 7) sorted by relevance
| /external/u-boot/arch/arm/mach-davinci/ |
| D | cpu.c | 39 int pll_out; in clk_get() local
42 pll_out = CONFIG_SYS_OSCIN_FREQ; in clk_get()
62 pll_out /= pre_div; in clk_get()
63 pll_out *= pllm; in clk_get()
71 pll_out /= post_div; in clk_get()
76 pll_out /= (readl(pll_base + sysdiv[id - 1]) & in clk_get()
80 return pll_out; in clk_get()
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| /external/u-boot/arch/arm/mach-tegra/ |
| D | clock.c | 286 clrsetbits_le32(&pll->pll_out[pllout >> 1], in clock_set_pllout()
795 writel(reg, &clkrst->crc_pll[CLOCK_ID_PERIPH].pll_out[0]); in tegra30_set_up_pllp()
801 writel(reg, &clkrst->crc_pll[CLOCK_ID_PERIPH].pll_out[0]); in tegra30_set_up_pllp()
806 writel(reg, &clkrst->crc_pll[CLOCK_ID_PERIPH].pll_out[1]); in tegra30_set_up_pllp()
812 writel(reg, &clkrst->crc_pll[CLOCK_ID_PERIPH].pll_out[1]); in tegra30_set_up_pllp()
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| /external/u-boot/arch/arm/mach-tegra/tegra210/ |
| D | clock.c | 944 writel(reg, &clkrst->crc_pll[CLOCK_ID_PERIPH].pll_out[0]); in tegra210_setup_pllp()
948 writel(reg, &clkrst->crc_pll[CLOCK_ID_PERIPH].pll_out[0]); in tegra210_setup_pllp()
953 writel(reg, &clkrst->crc_pll[CLOCK_ID_PERIPH].pll_out[1]); in tegra210_setup_pllp()
959 writel(reg, &clkrst->crc_pll[CLOCK_ID_PERIPH].pll_out[1]); in tegra210_setup_pllp()
1023 clrbits_le32(&clkrst->crc_pll[CLOCK_ID_CGENERAL].pll_out[1], in clock_early_init()
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| /external/u-boot/arch/arm/mach-tegra/tegra20/ |
| D | warmboot_avp.c | 202 writel(reg, &clkrst->crc_pll[CLOCK_ID_MEMORY].pll_out[0]); in wb_start()
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| /external/u-boot/arch/arm/include/asm/arch-tegra/ |
| D | clk_rst.h | 14 uint pll_out[2]; member
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| /external/u-boot/arch/arm/mach-tegra/tegra114/ |
| D | clock.c | 698 writel(0x00561600, &clkrst->crc_pll[CLOCK_ID_CGENERAL].pll_out[1]); in clock_early_init()
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| /external/u-boot/arch/arm/mach-tegra/tegra124/ |
| D | clock.c | 878 writel(0x00561600, &clkrst->crc_pll[CLOCK_ID_CGENERAL].pll_out[1]); in clock_early_init()
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