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/external/libxaac/decoder/armv7/
Dixheaacd_decorr_filter2.s39 LDR r10, [r13, #40]
51 ADD r10, r10, #12
58 STR r10, [r13, #-4]!
68 SUB r10, r11, #0x03A
75 STR r10, [r13, #-8]!
150 SMULTT r10, r7, r8
158 QSUB r9, r9, r10
159 LDR r10, [r1], #4
163 QADD r1, r10, r8
168 LDR r10, [r12], #4
[all …]
/external/swiftshader/third_party/llvm-7.0/llvm/test/MC/ARM/
Dldrd-strd-gnu-thumb.s8 @ CHECK: ldrd r0, r1, [r10, #512]! @ encoding: [0xfa,0xe9,0x80,0x01]
9 @ CHECK: ldrd r0, r1, [r10], #512 @ encoding: [0xfa,0xe8,0x80,0x01]
10 @ CHECK: ldrd r0, r1, [r10, #512] @ encoding: [0xda,0xe9,0x80,0x01]
11 ldrd r0, [r10, #512]!
12 ldrd r0, [r10], #512
13 ldrd r0, [r10, #512]
15 @ CHECK: strd r0, r1, [r10, #512]! @ encoding: [0xea,0xe9,0x80,0x01]
16 @ CHECK: strd r0, r1, [r10], #512 @ encoding: [0xea,0xe8,0x80,0x01]
17 @ CHECK: strd r0, r1, [r10, #512] @ encoding: [0xca,0xe9,0x80,0x01]
18 strd r0, [r10, #512]!
[all …]
/external/llvm/test/MC/X86/
Dx86_64-bmi-encoding.s9 blsmskq %r11, %r10
17 blsmskq (%rax), %r10
25 blsiq %r11, %r10
33 blsiq (%rax), %r10
41 blsrq %r11, %r10
49 blsrq (%rax), %r10
57 andnq (%rax), %r11, %r10
69 bextrq %r12, (%rax), %r10
73 bextrq %r12, %r11, %r10
85 bzhiq %r12, (%rax), %r10
[all …]
/external/swiftshader/third_party/llvm-7.0/llvm/test/MC/X86/
Dx86_64-bmi-encoding.s9 blsmskq %r11, %r10
17 blsmskq (%rax), %r10
25 blsiq %r11, %r10
33 blsiq (%rax), %r10
41 blsrq %r11, %r10
49 blsrq (%rax), %r10
57 andnq (%rax), %r11, %r10
69 bextrq %r12, (%rax), %r10
73 bextrq %r12, %r11, %r10
85 bzhiq %r12, (%rax), %r10
[all …]
/external/capstone/suite/MC/X86/
Dx86_64-bmi-encoding.s.cs3 0xc4,0xc2,0xa8,0xf3,0xd3 = blsmskq %r11, %r10
5 0xc4,0xe2,0xa8,0xf3,0x10 = blsmskq (%rax), %r10
7 0xc4,0xc2,0xa8,0xf3,0xdb = blsiq %r11, %r10
9 0xc4,0xe2,0xa8,0xf3,0x18 = blsiq (%rax), %r10
11 0xc4,0xc2,0xa8,0xf3,0xcb = blsrq %r11, %r10
13 0xc4,0xe2,0xa8,0xf3,0x08 = blsrq (%rax), %r10
15 0xc4,0x62,0xa0,0xf2,0x10 = andnq (%rax), %r11, %r10
18 0xc4,0x62,0x98,0xf7,0x10 = bextrq %r12, (%rax), %r10
19 0xc4,0x42,0x98,0xf7,0xd3 = bextrq %r12, %r11, %r10
22 0xc4,0x62,0x98,0xf5,0x10 = bzhiq %r12, (%rax), %r10
[all …]
/external/tremolo/Tremolo/
DbitwiseARM.s45 STMFD r13!,{r10,r11,r14}
53 LDR r10,[r3] @ r10= ptr[0]
57 MOV r10,r10,LSR r14 @ r10= ptr[0]>>(32-bitsLeftInWord)
60 ORRLT r10,r10,r11,LSL r14 @ r10= Next 32 bits.
63 AND r0,r10,r14
64 LDMFD r13!,{r10,r11,PC}
68 ADDS r10,r2,r1 @ r10= bitsLeftInSegment + bits (i.e.
70 @ r10 = bitsLeftInSegment (initial)
73 MOV r5,r10 @ r5 = bitsLeftInSegment (initial)
75 BEQ look_next_segment @ r10= r12 = 0, if we branch
[all …]
/external/python/cpython2/Modules/_ctypes/libffi/src/tile/
Dtile.S83 #define FRAME_SIZE r10
253 SW sp, r10
254 .cfi_return_column r10
255 .cfi_offset r10, 0
258 addli r10, sp, -(CLOSURE_FRAME_SIZE - REG_SIZE)
262 SW r10, sp
271 addi r10, sp, LINKAGE_SIZE
275 STORE_REG(r0, r10)
276 STORE_REG(r1, r10)
277 STORE_REG(r2, r10)
[all …]
/external/libffi/src/tile/
Dtile.S83 #define FRAME_SIZE r10
253 SW sp, r10
254 .cfi_return_column r10
255 .cfi_offset r10, 0
258 addli r10, sp, -(CLOSURE_FRAME_SIZE - REG_SIZE)
262 SW r10, sp
271 addi r10, sp, LINKAGE_SIZE
275 STORE_REG(r0, r10)
276 STORE_REG(r1, r10)
277 STORE_REG(r2, r10)
[all …]
/external/boringssl/ios-arm/crypto/fipsmodule/
Dsha1-armv4-large.S46 stmdb sp!,{r4,r5,r6,r7,r8,r9,r10,r11,r12,lr}
58 ldrb r10,[r1,#2]
63 orr r9,r9,r10,lsl#8
64 eor r10,r5,r6 @ F_xx_xx
71 eor r10,r5,r6 @ F_xx_xx
77 and r10,r4,r10,ror#2
79 eor r10,r10,r6,ror#2 @ F_00_19(B,C,D)
81 add r7,r7,r10 @ E+=F_00_19(B,C,D)
83 ldrb r10,[r1,#2]
88 orr r9,r9,r10,lsl#8
[all …]
/external/boringssl/linux-arm/crypto/fipsmodule/
Dsha1-armv4-large.S45 stmdb sp!,{r4,r5,r6,r7,r8,r9,r10,r11,r12,lr}
57 ldrb r10,[r1,#2]
62 orr r9,r9,r10,lsl#8
63 eor r10,r5,r6 @ F_xx_xx
70 eor r10,r5,r6 @ F_xx_xx
76 and r10,r4,r10,ror#2
78 eor r10,r10,r6,ror#2 @ F_00_19(B,C,D)
80 add r7,r7,r10 @ E+=F_00_19(B,C,D)
82 ldrb r10,[r1,#2]
87 orr r9,r9,r10,lsl#8
[all …]
/external/vixl/test/aarch32/
Dtest-assembler-rd-rn-rm-t32.cc100 {{{r2, r10, r12}, false, al, "r2 r10 r12", "r2_r10_r12"},
108 {{r4, r5, r10}, false, al, "r4 r5 r10", "r4_r5_r10"},
114 {{r10, r14, r3}, false, al, "r10 r14 r3", "r10_r14_r3"},
116 {{r12, r10, r12}, false, al, "r12 r10 r12", "r12_r10_r12"},
117 {{r4, r10, r12}, false, al, "r4 r10 r12", "r4_r10_r12"},
125 {{r14, r10, r13}, false, al, "r14 r10 r13", "r14_r10_r13"},
143 {{r3, r10, r4}, false, al, "r3 r10 r4", "r3_r10_r4"},
149 {{r13, r12, r10}, false, al, "r13 r12 r10", "r13_r12_r10"},
152 {{r10, r6, r12}, false, al, "r10 r6 r12", "r10_r6_r12"},
154 {{r7, r10, r5}, false, al, "r7 r10 r5", "r7_r10_r5"},
[all …]
Dtest-assembler-rd-rn-rm-a32.cc100 {{{r2, r10, r12}, false, al, "r2 r10 r12", "r2_r10_r12"},
108 {{r4, r5, r10}, false, al, "r4 r5 r10", "r4_r5_r10"},
114 {{r10, r14, r3}, false, al, "r10 r14 r3", "r10_r14_r3"},
116 {{r12, r10, r12}, false, al, "r12 r10 r12", "r12_r10_r12"},
117 {{r4, r10, r12}, false, al, "r4 r10 r12", "r4_r10_r12"},
125 {{r14, r10, r13}, false, al, "r14 r10 r13", "r14_r10_r13"},
143 {{r3, r10, r4}, false, al, "r3 r10 r4", "r3_r10_r4"},
149 {{r13, r12, r10}, false, al, "r13 r12 r10", "r13_r12_r10"},
152 {{r10, r6, r12}, false, al, "r10 r6 r12", "r10_r6_r12"},
154 {{r7, r10, r5}, false, al, "r7 r10 r5", "r7_r10_r5"},
[all …]
Dtest-macro-assembler-cond-rd-rn-t32.cc96 {{lt, r11, r10}, "lt, r11, r10", "lt_r11_r10"},
97 {{vs, r10, r8}, "vs, r10, r8", "vs_r10_r8"},
106 {{cc, r4, r10}, "cc, r4, r10", "cc_r4_r10"},
111 {{ls, r10, r10}, "ls, r10, r10", "ls_r10_r10"},
116 {{ge, r0, r10}, "ge, r0, r10", "ge_r0_r10"},
117 {{lt, r10, r6}, "lt, r10, r6", "lt_r10_r6"},
120 {{pl, r10, r6}, "pl, r10, r6", "pl_r10_r6"},
123 {{cc, r2, r10}, "cc, r2, r10", "cc_r2_r10"},
133 {{ne, r13, r10}, "ne, r13, r10", "ne_r13_r10"},
134 {{mi, r10, r9}, "mi, r10, r9", "mi_r10_r9"},
[all …]
Dtest-macro-assembler-cond-rd-rn-a32.cc96 {{lt, r11, r10}, "lt, r11, r10", "lt_r11_r10"},
97 {{vs, r10, r8}, "vs, r10, r8", "vs_r10_r8"},
106 {{cc, r4, r10}, "cc, r4, r10", "cc_r4_r10"},
111 {{ls, r10, r10}, "ls, r10, r10", "ls_r10_r10"},
116 {{ge, r0, r10}, "ge, r0, r10", "ge_r0_r10"},
117 {{lt, r10, r6}, "lt, r10, r6", "lt_r10_r6"},
120 {{pl, r10, r6}, "pl, r10, r6", "pl_r10_r6"},
123 {{cc, r2, r10}, "cc, r2, r10", "cc_r2_r10"},
133 {{ne, r13, r10}, "ne, r13, r10", "ne_r13_r10"},
134 {{mi, r10, r9}, "mi, r10, r9", "mi_r10_r9"},
[all …]
/external/boringssl/linux-x86_64/crypto/fipsmodule/
Dx86_64-mont5.S52 leaq -280(%rsp,%r9,8),%r10
54 andq $-1024,%r10
64 subq %r10,%r11
66 leaq (%r10,%r11,1),%rsp
68 cmpq %r10,%rsp
75 cmpq %r10,%rsp
79 leaq .Linc(%rip),%r10
85 movdqa 0(%r10),%xmm0
86 movdqa 16(%r10),%xmm1
87 leaq 24-112(%rsp,%r9,8),%r10
[all …]
/external/boringssl/mac-x86_64/crypto/fipsmodule/
Dx86_64-mont5.S51 leaq -280(%rsp,%r9,8),%r10
53 andq $-1024,%r10
63 subq %r10,%r11
65 leaq (%r10,%r11,1),%rsp
67 cmpq %r10,%rsp
74 cmpq %r10,%rsp
78 leaq L$inc(%rip),%r10
84 movdqa 0(%r10),%xmm0
85 movdqa 16(%r10),%xmm1
86 leaq 24-112(%rsp,%r9,8),%r10
[all …]
/external/libhevc/common/arm/
Dihevc_intra_pred_luma_mode_18_34.s126 mov r10,r2
160 vst1.8 {d0},[r10],r3
161 vst1.8 {d1},[r10],r3
163 vst1.8 {d2},[r10],r3
165 vst1.8 {d3},[r10],r3
168 vst1.8 {d4},[r10],r3
170 vst1.8 {d5},[r10],r3
172 vst1.8 {d6},[r10],r3
174 vst1.8 {d7},[r10],r3
177 subeq r2,r10,r14
[all …]
/external/boringssl/ios-arm/crypto/chacha/
Dchacha-armv4.S84 ldmia r3,{r4,r5,r6,r7,r8,r9,r10,r11} @ load key
86 stmdb sp!,{r4,r5,r6,r7,r8,r9,r10,r11} @ copy key
88 str r10,[sp,#4*(16+10)] @ off-load "rx"
101 ldr r10, [sp,#4*(13)]
113 mov r10,r10,ror#16
115 eor r10,r10,r1,ror#16
118 add r9,r9,r10
125 mov r10,r10,ror#24
127 eor r10,r10,r1,ror#24
130 add r9,r9,r10
[all …]
/external/boringssl/linux-arm/crypto/chacha/
Dchacha-armv4.S83 ldmia r3,{r4,r5,r6,r7,r8,r9,r10,r11} @ load key
85 stmdb sp!,{r4,r5,r6,r7,r8,r9,r10,r11} @ copy key
87 str r10,[sp,#4*(16+10)] @ off-load "rx"
100 ldr r10, [sp,#4*(13)]
112 mov r10,r10,ror#16
114 eor r10,r10,r1,ror#16
117 add r9,r9,r10
124 mov r10,r10,ror#24
126 eor r10,r10,r1,ror#24
129 add r9,r9,r10
[all …]
/external/boringssl/src/crypto/fipsmodule/bn/asm/
Dx86_64-mont5.pl64 $lo0="%r10";
113 lea -280(%rsp,$num,8),%r10 # future alloca(8*(num+2)+256+8)
115 and \$-1024,%r10 # minimize TLB usage
125 sub %r10,%r11
127 lea (%r10,%r11),%rsp
129 cmp %r10,%rsp
136 cmp %r10,%rsp
140 lea .Linc(%rip),%r10
151 movdqa 0(%r10),%xmm0 # 00000001000000010000000000000000
152 movdqa 16(%r10),%xmm1 # 00000002000000020000000200000002
[all …]
/external/swiftshader/third_party/llvm-7.0/llvm/test/CodeGen/XCore/
Dllvm-intrinsics.ll158 ; CHECKFP: stw r10, sp[1]
159 ; CHECKFP: ldaw r10, sp[0]
160 ; CHECKFP: stw r4, r10[9]
161 ; CHECKFP: stw r5, r10[8]
162 ; CHECKFP: stw r6, r10[7]
163 ; CHECKFP: stw r7, r10[6]
164 ; CHECKFP: stw r8, r10[5]
165 ; CHECKFP: stw r9, r10[4]
166 ; CHECKFP: ldw r9, r10[4]
167 ; CHECKFP: ldw r8, r10[5]
[all …]
/external/llvm/test/CodeGen/XCore/
Dllvm-intrinsics.ll158 ; CHECKFP: stw r10, sp[1]
159 ; CHECKFP: ldaw r10, sp[0]
160 ; CHECKFP: stw r4, r10[9]
161 ; CHECKFP: stw r5, r10[8]
162 ; CHECKFP: stw r6, r10[7]
163 ; CHECKFP: stw r7, r10[6]
164 ; CHECKFP: stw r8, r10[5]
165 ; CHECKFP: stw r9, r10[4]
166 ; CHECKFP: ldw r9, r10[4]
167 ; CHECKFP: ldw r8, r10[5]
[all …]
/external/libffi/src/x86/
Dunix64.S49 movq (%rsp), %r10 /* Load return address. */
54 movq %r10, 24(%rax) /* Relocate return address. */
57 movq %rdi, %r10 /* Save a copy of the register area. */
62 movq (%r10), %rdi
63 movq 8(%r10), %rsi
64 movq 16(%r10), %rdx
65 movq 24(%r10), %rcx
66 movq 32(%r10), %r8
67 movq 40(%r10), %r9
73 leaq 176(%r10), %rsp
[all …]
/external/python/cpython2/Modules/_ctypes/libffi/src/x86/
Dunix64.S49 movq (%rsp), %r10 /* Load return address. */
54 movq %r10, 24(%rax) /* Relocate return address. */
57 movq %rdi, %r10 /* Save a copy of the register area. */
62 movq (%r10), %rdi
63 movq 8(%r10), %rsi
64 movq 16(%r10), %rdx
65 movq 24(%r10), %rcx
66 movq 32(%r10), %r8
67 movq 40(%r10), %r9
73 leaq 176(%r10), %rsp
[all …]
/external/llvm/test/MC/ARM/
Dldrd-strd-gnu-thumb.s8 @ CHECK: ldrd r0, r1, [r10, #512]! @ encoding: [0xfa,0xe9,0x80,0x01]
9 @ CHECK: ldrd r0, r1, [r10], #512 @ encoding: [0xfa,0xe8,0x80,0x01]
10 @ CHECK: ldrd r0, r1, [r10, #512] @ encoding: [0xda,0xe9,0x80,0x01]
11 ldrd r0, [r10, #512]!
12 ldrd r0, [r10], #512
13 ldrd r0, [r10, #512]
15 @ CHECK: strd r0, r1, [r10, #512]! @ encoding: [0xea,0xe9,0x80,0x01]
16 @ CHECK: strd r0, r1, [r10], #512 @ encoding: [0xea,0xe8,0x80,0x01]
17 @ CHECK: strd r0, r1, [r10, #512] @ encoding: [0xca,0xe9,0x80,0x01]
18 strd r0, [r10, #512]!
[all …]

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