| /external/lzma/Asm/x86/ |
| D | XzCrc64Opt.asm | 10 rD equ r9 define
16 SRCDAT equ rN + rD
23 movzx x6, BYTE PTR [rD]
24 inc rD
38 mov rD, r2
42 test rD, 3
49 add rN, rD
53 sub rD, rN
63 mov rD, rN
65 sub rN, rD
[all …]
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| D | 7zCrcOpt.asm | 8 rD equ r2 define
21 SRCDAT equ rN + rD + 4 *
36 movzx x6, BYTE PTR [rD]
37 inc rD
54 test rD, 7
61 add rN, rD
65 sub rD, rN
71 mov rD, rN
73 sub rN, rD
110 add rD, 8
[all …]
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| /external/llvm/lib/Target/PowerPC/ |
| D | PPCInstr64Bit.td | 240 def LDARX : XForm_1<31, 84, (outs g8rc:$rD), (ins memrr:$ptr),
241 "ldarx $rD, $ptr", IIC_LdStLDARX, []>;
245 def LDARXL : XForm_1<31, 84, (outs g8rc:$rD), (ins memrr:$ptr),
246 "ldarx $rD, $ptr, 1", IIC_LdStLDARX, []>, isDOT;
249 def LDAT : X_RD5_RS5_IM5<31, 614, (outs g8rc:$rD), (ins g8rc:$rA, u5imm:$FC),
250 "ldat $rD, $rA, $FC", IIC_LdStLoad>, isPPC64,
420 def LI8 : DForm_2_r0<14, (outs g8rc:$rD), (ins s16imm64:$imm),
421 "li $rD, $imm", IIC_IntSimple,
422 [(set i64:$rD, imm64SExt16:$imm)]>;
423 def LIS8 : DForm_2_r0<15, (outs g8rc:$rD), (ins s17imm64:$imm),
[all …]
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| D | PPCInstrInfo.td | 1073 def UPDATE_VRSAVE : Pseudo<(outs gprc:$rD), (ins gprc:$rS),
1074 "UPDATE_VRSAVE $rD, $rS", []>;
1436 def MFBHRBE : XFXForm_3p<31, 302, (outs gprc:$rD),
1438 "mfbhrbe $rD, $imm", IIC_BrB,
1439 [(set i32:$rD,
1573 def LBARX : XForm_1<31, 52, (outs gprc:$rD), (ins memrr:$src),
1574 "lbarx $rD, $src", IIC_LdStLWARX, []>,
1577 def LHARX : XForm_1<31, 116, (outs gprc:$rD), (ins memrr:$src),
1578 "lharx $rD, $src", IIC_LdStLWARX, []>,
1581 def LWARX : XForm_1<31, 20, (outs gprc:$rD), (ins memrr:$src),
[all …]
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| D | README_P9.txt | 23 (set i64:$rD, (int_ppc_altivec_vextublx i64:$rA, v16i8:$vB))
24 (set i64:$rD, (int_ppc_altivec_vextuhlx i64:$rA, v8i16:$vB))
25 (set i64:$rD, (int_ppc_altivec_vextuwlx i64:$rA, v4i32:$vB))
28 (set i64:$rD, (int_ppc_altivec_vextubrx i64:$rA, v16i8:$vB))
29 (set i64:$rD, (int_ppc_altivec_vextuhrx i64:$rA, v8i16:$vB))
30 (set i64:$rD, (int_ppc_altivec_vextuwrx i64:$rA, v4i32:$vB))
38 - Vector Count Leading/Trailing Zero LSB. Result is placed into GPR[rD]:
41 (set i64:$rD, (int_ppc_altivec_vclzlsbb v16i8:$vB))
42 (set i64:$rD, (int_ppc_altivec_vctzlsbb v16i8:$vB))
99 (set v4i32:$rD, (int_ppc_altivec_vprtybw v4i32:$vB))
[all …]
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| /external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/PowerPC/ |
| D | PPCInstr64Bit.td | 247 def LDARX : XForm_1_memOp<31, 84, (outs g8rc:$rD), (ins memrr:$ptr),
248 "ldarx $rD, $ptr", IIC_LdStLDARX, []>;
252 def LDARXL : XForm_1<31, 84, (outs g8rc:$rD), (ins memrr:$ptr),
253 "ldarx $rD, $ptr, 1", IIC_LdStLDARX, []>, isDOT;
256 def LDAT : X_RD5_RS5_IM5<31, 614, (outs g8rc:$rD), (ins g8rc:$rA, u5imm:$FC),
257 "ldat $rD, $rA, $FC", IIC_LdStLoad>, isPPC64,
427 def LI8 : DForm_2_r0<14, (outs g8rc:$rD), (ins s16imm64:$imm),
428 "li $rD, $imm", IIC_IntSimple,
429 [(set i64:$rD, imm64SExt16:$imm)]>;
430 def LIS8 : DForm_2_r0<15, (outs g8rc:$rD), (ins s17imm64:$imm),
[all …]
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| D | PPCInstrInfo.td | 1204 def UPDATE_VRSAVE : Pseudo<(outs gprc:$rD), (ins gprc:$rS),
1205 "UPDATE_VRSAVE $rD, $rS", []>;
1581 def MFBHRBE : XFXForm_3p<31, 302, (outs gprc:$rD),
1583 "mfbhrbe $rD, $imm", IIC_BrB,
1584 [(set i32:$rD,
1773 def LBARX : XForm_1_memOp<31, 52, (outs gprc:$rD), (ins memrr:$src),
1774 "lbarx $rD, $src", IIC_LdStLWARX, []>,
1777 def LHARX : XForm_1_memOp<31, 116, (outs gprc:$rD), (ins memrr:$src),
1778 "lharx $rD, $src", IIC_LdStLWARX, []>,
1781 def LWARX : XForm_1_memOp<31, 20, (outs gprc:$rD), (ins memrr:$src),
[all …]
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| D | README_P9.txt | 23 (set i64:$rD, (int_ppc_altivec_vextublx i64:$rA, v16i8:$vB))
24 (set i64:$rD, (int_ppc_altivec_vextuhlx i64:$rA, v8i16:$vB))
25 (set i64:$rD, (int_ppc_altivec_vextuwlx i64:$rA, v4i32:$vB))
28 (set i64:$rD, (int_ppc_altivec_vextubrx i64:$rA, v16i8:$vB))
29 (set i64:$rD, (int_ppc_altivec_vextuhrx i64:$rA, v8i16:$vB))
30 (set i64:$rD, (int_ppc_altivec_vextuwrx i64:$rA, v4i32:$vB))
38 - Vector Count Leading/Trailing Zero LSB. Result is placed into GPR[rD]:
41 (set i64:$rD, (int_ppc_altivec_vclzlsbb v16i8:$vB))
42 (set i64:$rD, (int_ppc_altivec_vctzlsbb v16i8:$vB))
99 (set v4i32:$rD, (int_ppc_altivec_vprtybw v4i32:$vB))
[all …]
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| /external/honggfuzz/examples/apache-httpd/corpus_http1/ |
| D | aa3223194649ad6703eec88a8863a844.00000227.honggfuzz.cov | 8 ��(rD�digFsT
13 ��(rD�digFsT
17 . � ��ݣ�{ ������(rD�S��]�on:digFsT
22 ��(rD�S��]�on:PigFsT
29 ��(rD�S��]�on:PigFsT
36 ��(rD�S��]�on:digFsT
|
| D | f28b4d1450edfb432f42634a96e5abae.0000018c.honggfuzz.cov | 8 ��(rD�digFsT
12 . � ��ݣ�{ ������(rD�S��]�on:digFsT
17 ��(rD�S��]�on:PigFsT
24 ��(rD�S��]�on:digFsT
|
| /external/honggfuzz/examples/apache-httpd/corpus_http2/ |
| D | aa3223194649ad6703eec88a8863a844.00000227.honggfuzz.cov | 8 ��(rD�digFsT
13 ��(rD�digFsT
17 . � ��ݣ�{ ������(rD�S��]�on:digFsT
22 ��(rD�S��]�on:PigFsT
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|
| D | f28b4d1450edfb432f42634a96e5abae.0000018c.honggfuzz.cov | 8 ��(rD�digFsT
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17 ��(rD�S��]�on:PigFsT
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|
| /external/aac/libFDK/src/ |
| D | FDK_crc.cpp | 429 CCrcRegData *rD = &hCrcInfo->crcRegData[reg]; in crcCalc() local
435 -(rD->validBits - (INT)FDKgetValidBits(&bsReader))); in crcCalc()
439 FDKpushBiDirectional(&bsReader, rD->validBits); in crcCalc()
443 rBits = (rD->maxBits >= 0) ? rD->maxBits : -rD->maxBits; /* ramaining bits */ in crcCalc()
444 if ((rD->maxBits > 0) && ((rD->bitBufCntBits >> 3 << 3) < rBits)) { in crcCalc()
445 bits = rD->bitBufCntBits; in crcCalc()
|
| /external/swiftshader/third_party/subzero/tests_lit/llvm2ice_tests/ |
| D | reorder-global-variables.ll | 7 ; RUN: -i %s --assemble --disassemble --dis-flags=-rD \
11 ; RUN: -i %s --assemble --disassemble --dis-flags=-rD \
17 ; RUN: -i %s --disassemble --dis-flags=-rD \
21 ; RUN: -i %s --disassemble --dis-flags=-rD \
27 ; RUN: -i %s --disassemble --dis-flags=-rD \
32 ; RUN: -i %s --disassemble --dis-flags=-rD \
39 ; RUN: mips32 -i %s --dis-flags=-rD --args -O2 -sz-seed=1 \
|
| /external/compiler-rt/lib/builtins/arm/ |
| D | sync-ops.h | 51 #define MINMAX_4(rD, rN, rM, cmp_kind) \ argument
53 mov rD, rM ; \
55 mov##cmp_kind rD, rN
|
| D | sync_fetch_and_or_4.S | 17 #define or_4(rD, rN, rM) orr rD, rN, rM argument
|
| D | sync_fetch_and_add_4.S | 18 #define add_4(rD, rN, rM) add rD, rN, rM argument
|
| D | sync_fetch_and_and_4.S | 17 #define and_4(rD, rN, rM) and rD, rN, rM argument
|
| D | sync_fetch_and_nand_4.S | 17 #define nand_4(rD, rN, rM) bic rD, rN, rM argument
|
| D | sync_fetch_and_xor_4.S | 17 #define xor_4(rD, rN, rM) eor rD, rN, rM argument
|
| D | sync_fetch_and_sub_4.S | 18 #define sub_4(rD, rN, rM) sub rD, rN, rM argument
|
| D | sync_fetch_and_min_4.S | 17 #define min_4(rD, rN, rM) MINMAX_4(rD, rN, rM, lt) argument
|
| D | sync_fetch_and_umax_4.S | 17 #define umax_4(rD, rN, rM) MINMAX_4(rD, rN, rM, hi) argument
|
| D | sync_fetch_and_umin_4.S | 17 #define umin_4(rD, rN, rM) MINMAX_4(rD, rN, rM, lo) argument
|
| D | sync_fetch_and_max_4.S | 17 #define max_4(rD, rN, rM) MINMAX_4(rD, rN, rM, gt) argument
|