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Searched refs:rcs (Results 1 – 25 of 73) sorted by relevance

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/external/mesa3d/src/gallium/winsys/radeon/drm/
Dradeon_drm_cs.c69 static struct pipe_fence_handle *radeon_cs_create_fence(struct radeon_cmdbuf *rcs);
350 static unsigned radeon_drm_cs_add_buffer(struct radeon_cmdbuf *rcs, in radeon_drm_cs_add_buffer() argument
356 struct radeon_drm_cs *cs = radeon_drm_cs(rcs); in radeon_drm_cs_add_buffer()
397 static int radeon_drm_cs_lookup_buffer(struct radeon_cmdbuf *rcs, in radeon_drm_cs_lookup_buffer() argument
400 struct radeon_drm_cs *cs = radeon_drm_cs(rcs); in radeon_drm_cs_lookup_buffer()
405 static bool radeon_drm_cs_validate(struct radeon_cmdbuf *rcs) in radeon_drm_cs_validate() argument
407 struct radeon_drm_cs *cs = radeon_drm_cs(rcs); in radeon_drm_cs_validate()
444 static bool radeon_drm_cs_check_space(struct radeon_cmdbuf *rcs, unsigned dw, in radeon_drm_cs_check_space() argument
447 assert(rcs->current.cdw <= rcs->current.max_dw); in radeon_drm_cs_check_space()
448 return rcs->current.max_dw - rcs->current.cdw >= dw; in radeon_drm_cs_check_space()
[all …]
Dradeon_drm_cs.h139 void radeon_drm_cs_sync_flush(struct radeon_cmdbuf *rcs);
/external/mesa3d/src/gallium/winsys/amdgpu/drm/
Damdgpu_cs.c257 amdgpu_cs_get_next_fence(struct radeon_cmdbuf *rcs) in amdgpu_cs_get_next_fence() argument
259 struct amdgpu_cs *cs = amdgpu_cs(rcs); in amdgpu_cs_get_next_fence()
622 static unsigned amdgpu_cs_add_buffer(struct radeon_cmdbuf *rcs, in amdgpu_cs_add_buffer() argument
631 struct amdgpu_cs *acs = amdgpu_cs(rcs); in amdgpu_cs_add_buffer()
1035 amdgpu_cs_setup_preemption(struct radeon_cmdbuf *rcs, const uint32_t *preamble_ib, in amdgpu_cs_setup_preemption() argument
1038 struct amdgpu_ib *ib = amdgpu_ib(rcs); in amdgpu_cs_setup_preemption()
1083 amdgpu_cs_add_buffer(rcs, cs->preamble_ib_bo, RADEON_USAGE_READ, 0, in amdgpu_cs_setup_preemption()
1088 static bool amdgpu_cs_validate(struct radeon_cmdbuf *rcs) in amdgpu_cs_validate() argument
1093 static bool amdgpu_cs_check_space(struct radeon_cmdbuf *rcs, unsigned dw, in amdgpu_cs_check_space() argument
1096 struct amdgpu_ib *ib = amdgpu_ib(rcs); in amdgpu_cs_check_space()
[all …]
Damdgpu_winsys.c188 static bool amdgpu_cs_request_feature(struct radeon_cmdbuf *rcs, in amdgpu_cs_request_feature() argument
331 static bool amdgpu_cs_is_secure(struct radeon_cmdbuf *rcs) in amdgpu_cs_is_secure() argument
333 struct amdgpu_cs *cs = amdgpu_cs(rcs); in amdgpu_cs_is_secure()
Damdgpu_bo.h135 struct radeon_cmdbuf *rcs,
/external/scapy/scapy/layers/tls/
Drecord.py134 if False in six.itervalues(pkt.tls_session.rcs.cipher.ready):
288 if s.rcs and not isinstance(s.rcs.cipher, Cipher_NULL):
309 read_seq_num = struct.pack("!Q", self.tls_session.rcs.seq_num)
310 self.tls_session.rcs.seq_num += 1
315 return self.tls_session.rcs.cipher.auth_decrypt(add_data, s,
332 return self.tls_session.rcs.cipher.decrypt(s)
345 read_seq_num = struct.pack("!Q", self.tls_session.rcs.seq_num)
346 self.tls_session.rcs.seq_num += 1
348 mac_len = self.tls_session.rcs.mac_len
354 alg = self.tls_session.rcs.hmac
[all …]
Drecord_tls13.py71 tag_len = pkt.tls_session.rcs.mac_len
112 rcs = self.tls_session.rcs
113 read_seq_num = struct.pack("!Q", rcs.seq_num)
114 rcs.seq_num += 1
116 return rcs.cipher.auth_decrypt(b"", s, read_seq_num)
131 if isinstance(self.tls_session.rcs.cipher, Cipher_NULL):
149 self.tls_session.rcs = self.tls_session.prcs
188 if not isinstance(self.tls_session.rcs.cipher, Cipher_NULL):
Dbasefields.py119 cipher_type = pkt.tls_session.rcs.cipher.type
122 l = pkt.tls_session.rcs.cipher.block_size
124 l = pkt.tls_session.rcs.cipher.nonce_explicit_len
135 cipher_type = pkt.tls_session.rcs.cipher.type
138 l = pkt.tls_session.rcs.cipher.block_size
140 l = pkt.tls_session.rcs.cipher.nonce_explicit_len
163 if (pkt.tls_session.rcs.cipher.type != "aead" and
164 False in six.itervalues(pkt.tls_session.rcs.cipher.ready)):
167 l = pkt.tls_session.rcs.mac_len
Drecord_sslv2.py86 secret = self.tls_session.rcs.cipher.key
90 mac_len = self.tls_session.rcs.mac_len
96 read_seq_num = struct.pack("!I", self.tls_session.rcs.seq_num)
97 alg = self.tls_session.rcs.hash
120 cipher_type = self.tls_session.rcs.cipher.type
126 maclen = self.tls_session.rcs.mac_len
156 self.tls_session.rcs = self.tls_session.prcs
167 self.tls_session.rcs.seq_num += 1
264 self.tls_session.rcs = self.tls_session.prcs
Dsession.py310 wcs=None, rcs=None): argument
335 if rcs is None:
337 self.rcs = readConnState(connection_end=connection_end)
338 self.rcs.derive_keys()
340 self.rcs = rcs
460 if hasattr(self, "rcs") and self.rcs:
461 self.rcs.connection_end = val
497 self.rcs, self.wcs = self.wcs, self.rcs
498 if self.rcs:
499 self.rcs.row = "read"
[all …]
/external/igt-gpu-tools/tests/i915/
Dgem_read_read_speed.c128 drm_intel_bo *src = NULL, *bcs = NULL, *rcs = NULL; in run() local
138 rcs = create_bo(bufmgr, "rcs"); in run()
148 rcs_batch = rcs_copy_bo(src, rcs); in run()
150 rcs_batch = rcs_copy_bo(rcs, src); in run()
153 drm_intel_bo_unreference(rcs); in run()
Dgem_ppgtt.c302 drm_intel_bo *bcs[1], *rcs[N_CHILD]; variable
305 fork_rcs_copy(30, 0x8000 / N_CHILD, rcs, N_CHILD, 0);
310 surfaces_check(rcs, N_CHILD, 0x8000 / N_CHILD);
314 drm_intel_bo *bcs[1], *rcs[N_CHILD]; variable
316 fork_rcs_copy(30, 0x8000 / N_CHILD, rcs, N_CHILD, CREATE_CONTEXT);
322 surfaces_check(rcs, N_CHILD, 0x8000 / N_CHILD);
/external/iproute2/lib/
DMakefile14 $(QUIET_AR)$(AR) rcs $@ $^
17 $(QUIET_AR)$(AR) rcs $@ $^
/external/igt-gpu-tools/benchmarks/ezbench.d/
Dgem_exec_fault.test4 ring=rcs # rcs bcs vcs vecs all
Dgem_prw.test6 # gem_exec_nop:rcs, gem_exec_nop:bcs, gem_exec_nop:vcs
Dgem_exec_nop.test4 for ring in rcs bcs vcs vecs all; do
Dgem_busy.test4 for ring in rcs bcs vcs vecs all; do
/external/mesa3d/src/amd/vulkan/winsys/null/
Dradv_null_cs.c86 static void radv_null_cs_destroy(struct radeon_cmdbuf *rcs) in radv_null_cs_destroy() argument
88 struct radv_null_cs *cs = radv_null_cs(rcs); in radv_null_cs_destroy()
/external/swiftshader/third_party/llvm-7.0/llvm/test/Object/X86/
Darchive-symbol-table.s3 # RUN: llvm-ar rcs %t %t.o
Darchive-ir-asm.ll3 ; RUN: llvm-ar rcs %t2 %t1
/external/ltp/testcases/commands/nm/datafiles/
DMakefile22 $(AR) rcs $@ $?
/external/oss-fuzz/infra/base-images/base-builder/
Dprecompile_honggfuzz39 ar rcs $PRECOMPILED_DIR/honggfuzz.a libhfuzz/*.o libhfcommon/*.o
/external/llvm/test/Object/X86/
Darchive-ir-asm.ll3 ; RUN: llvm-ar rcs %t2 %t1
/external/grpc-grpc/templates/
DMakefile.template157 AR = ar rcs
169 AR = ar rcs
174 AR = ar rcs
/external/mesa3d/src/amd/vulkan/winsys/amdgpu/
Dradv_amdgpu_cs.c278 static void radv_amdgpu_cs_destroy(struct radeon_cmdbuf *rcs) in radv_amdgpu_cs_destroy() argument
280 struct radv_amdgpu_cs *cs = radv_amdgpu_cs(rcs); in radv_amdgpu_cs_destroy()
291 struct radeon_cmdbuf *rcs = &cs->old_cs_buffers[i]; in radv_amdgpu_cs_destroy() local
292 free(rcs->buf); in radv_amdgpu_cs_destroy()
540 struct radeon_cmdbuf *rcs = &cs->old_cs_buffers[i]; in radv_amdgpu_cs_reset() local
541 free(rcs->buf); in radv_amdgpu_cs_reset()
1127 struct radeon_cmdbuf *rcs = new_cs_array[j]; in radv_amdgpu_winsys_cs_submit_sysmem() local
1133 size += rcs->cdw; in radv_amdgpu_winsys_cs_submit_sysmem()
1155 memcpy(ptr, rcs->buf, 4 * rcs->cdw); in radv_amdgpu_winsys_cs_submit_sysmem()
1156 ptr += rcs->cdw; in radv_amdgpu_winsys_cs_submit_sysmem()

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