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Searched refs:read_mpidr_el1 (Results 1 – 25 of 49) sorted by relevance

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/external/arm-trusted-firmware/plat/amlogic/gxl/
Dgxl_pm.c50 u_register_t mpidr = read_mpidr_el1(); in gxl_system_reset()
81 u_register_t mpidr = read_mpidr_el1(); in gxl_system_off()
130 unsigned int core = plat_calc_core_pos(read_mpidr_el1()); in gxl_pwr_domain_on_finish()
149 u_register_t mpidr = read_mpidr_el1(); in gxl_pwr_domain_off()
165 u_register_t mpidr = read_mpidr_el1(); in gxl_pwr_domain_pwr_down_wfi()
/external/arm-trusted-firmware/plat/amlogic/g12a/
Dg12a_pm.c50 u_register_t mpidr = read_mpidr_el1(); in g12a_system_reset()
81 u_register_t mpidr = read_mpidr_el1(); in g12a_system_off()
130 unsigned int core = plat_calc_core_pos(read_mpidr_el1()); in g12a_pwr_domain_on_finish()
149 u_register_t mpidr = read_mpidr_el1(); in g12a_pwr_domain_off()
166 u_register_t mpidr = read_mpidr_el1(); in g12a_pwr_domain_pwr_down_wfi()
/external/arm-trusted-firmware/plat/arm/board/fvp/
Dfvp_pm.c56 uint64_t mpidr = read_mpidr_el1(); in fvp_cluster_pwrdwn_common()
93 mpidr = read_mpidr_el1(); in fvp_power_domain_on_finish_common()
185 fvp_pwrc_write_ppoffr(read_mpidr_el1()); in fvp_pwr_domain_off()
213 mpidr = read_mpidr_el1(); in fvp_pwr_domain_suspend()
238 fvp_pwrc_write_ppoffr(read_mpidr_el1()); in fvp_pwr_domain_suspend()
Dfvp_common.c182 mpidr = read_mpidr_el1(); in get_interconnect_master()
333 if ((read_mpidr_el1() & MPIDR_MT_MASK) != 0U) in fvp_config_setup()
Dfvp_topology.c95 mpidr |= (read_mpidr_el1() & MPIDR_MT_MASK); in plat_core_pos_by_mpidr()
/external/arm-trusted-firmware/plat/amlogic/gxbb/
Dgxbb_pm.c77 gxbb_program_mailbox(read_mpidr_el1(), 0); in gxbb_system_off()
114 unsigned int core = plat_calc_core_pos(read_mpidr_el1()); in gxbb_pwr_domain_on_finish()
132 u_register_t mpidr = read_mpidr_el1(); in gxbb_pwr_domain_off()
152 unsigned int core = plat_calc_core_pos(read_mpidr_el1()); in gxbb_pwr_domain_pwr_down_wfi()
/external/arm-trusted-firmware/plat/hisilicon/hikey960/
Dhikey960_pm.c85 cci_enable_snoop_dvm_reqs(MPIDR_AFFLVL1_VAL(read_mpidr_el1())); in hikey960_pwr_domain_on_finish()
93 unsigned long mpidr = read_mpidr_el1(); in hikey960_pwr_domain_off()
110 cci_disable_snoop_dvm_reqs(MPIDR_AFFLVL1_VAL(read_mpidr_el1())); in hikey960_pwr_domain_off()
182 u_register_t mpidr = read_mpidr_el1(); in hikey960_pwr_domain_suspend()
258 unsigned long mpidr = read_mpidr_el1(); in hikey960_pwr_domain_suspend_finish()
/external/arm-trusted-firmware/plat/renesas/rcar/
Dplat_pm.c78 unsigned long mpidr = read_mpidr_el1(); in rcar_pwr_domain_on_finish()
96 unsigned long mpidr = read_mpidr_el1(); in rcar_pwr_domain_off()
114 unsigned long mpidr = read_mpidr_el1(); in rcar_pwr_domain_suspend()
173 uint64_t cpu = read_mpidr_el1() & 0x0000ffff; in rcar_system_off()
266 unsigned long mpidr = read_mpidr_el1() & 0x0000ffffU; in rcar_get_sys_suspend_power_state()
/external/arm-trusted-firmware/plat/socionext/synquacer/
Dsq_ccn.c36 ccn_enter_snoop_dvm_domain(1 << MPIDR_AFFLVL1_VAL(read_mpidr_el1())); in plat_sq_interconnect_enter_coherency()
44 ccn_exit_snoop_dvm_domain(1 << MPIDR_AFFLVL1_VAL(read_mpidr_el1())); in plat_sq_interconnect_exit_coherency()
/external/arm-trusted-firmware/plat/marvell/common/
Dmarvell_cci.c42 cci_enable_snoop_dvm_reqs(MPIDR_AFFLVL1_VAL(read_mpidr_el1())); in plat_marvell_interconnect_enter_coherency()
51 cci_disable_snoop_dvm_reqs(MPIDR_AFFLVL1_VAL(read_mpidr_el1())); in plat_marvell_interconnect_exit_coherency()
/external/arm-trusted-firmware/plat/arm/common/
Darm_cci.c41 cci_enable_snoop_dvm_reqs(MPIDR_AFFLVL1_VAL(read_mpidr_el1())); in plat_arm_interconnect_enter_coherency()
49 cci_disable_snoop_dvm_reqs(MPIDR_AFFLVL1_VAL(read_mpidr_el1())); in plat_arm_interconnect_exit_coherency()
Darm_ccn.c48 ccn_enter_snoop_dvm_domain(1 << MPIDR_AFFLVL1_VAL(read_mpidr_el1())); in plat_arm_interconnect_enter_coherency()
56 ccn_exit_snoop_dvm_domain(1 << MPIDR_AFFLVL1_VAL(read_mpidr_el1())); in plat_arm_interconnect_exit_coherency()
/external/arm-trusted-firmware/plat/mediatek/mt6795/
Dplat_pm.c282 unsigned long mpidr = read_mpidr_el1(); in plat_affinst_off()
317 unsigned long mpidr = read_mpidr_el1(); in plat_affinst_suspend()
363 unsigned long mpidr = read_mpidr_el1(); in plat_affinst_on_finish()
391 unsigned long mpidr = read_mpidr_el1(); in plat_affinst_suspend_finish()
/external/arm-trusted-firmware/plat/imx/imx8m/
Dimx8m_psci_common.c60 uint64_t mpidr = read_mpidr_el1(); in imx_pwr_domain_off()
105 uint64_t mpidr = read_mpidr_el1(); in imx_domain_suspend()
127 uint64_t mpidr = read_mpidr_el1(); in imx_domain_suspend_finish()
/external/arm-trusted-firmware/plat/socionext/uniphier/
Duniphier_cci.c27 cci_enable_snoop_dvm_reqs(MPIDR_AFFLVL1_VAL(read_mpidr_el1())); in __uniphier_cci_enable()
32 cci_disable_snoop_dvm_reqs(MPIDR_AFFLVL1_VAL(read_mpidr_el1())); in __uniphier_cci_disable()
/external/arm-trusted-firmware/services/std_svc/sdei/
Dsdei_main.c78 SDEI_LOG("Private events initialized on %lx\n", read_mpidr_el1()); in sdei_cpu_on_init()
89 SDEI_LOG("Events masked on %lx\n", read_mpidr_el1()); in sdei_cpu_wakeup_init()
981 SDEI_LOG("> CTX(p:%d):%lx\n", (int) x1, read_mpidr_el1()); in sdei_smc_handler()
992 (unsigned int) resume, x1, read_mpidr_el1()); in sdei_smc_handler()
1027 SDEI_LOG("> UNMASK:%lx\n", read_mpidr_el1()); in sdei_smc_handler()
1033 SDEI_LOG("> MASK:%lx\n", read_mpidr_el1()); in sdei_smc_handler()
1051 SDEI_LOG("> S_RESET():%lx\n", read_mpidr_el1()); in sdei_smc_handler()
1057 SDEI_LOG("> P_RESET():%lx\n", read_mpidr_el1()); in sdei_smc_handler()
Dsdei_intr_mgmt.c80 uint64_t my_mpidr = read_mpidr_el1() & MPIDR_AFFINITY_MASK; in sdei_pe_unmask()
288 uint64_t my_mpidr __unused = (read_mpidr_el1() & MPIDR_AFFINITY_MASK); in handle_masked_trigger()
351 const uint64_t mpidr = read_mpidr_el1(); in sdei_intr_handler()
641 SDEI_LOG("EOI:%lx, %d spsr:%lx elr:%lx\n", read_mpidr_el1(), in sdei_event_complete()
/external/arm-trusted-firmware/plat/mediatek/mt8173/
Dplat_pm.c292 unsigned long mpidr = read_mpidr_el1(); in plat_power_domain_off()
323 unsigned long mpidr = read_mpidr_el1(); in plat_power_domain_suspend()
372 unsigned long mpidr = read_mpidr_el1(); in plat_power_domain_on_finish()
402 unsigned long mpidr = read_mpidr_el1(); in plat_power_domain_suspend_finish()
/external/arm-trusted-firmware/plat/imx/imx8qm/
Dimx8qm_psci.c105 uint64_t mpidr = read_mpidr_el1(); in imx_pwr_domain_on_finish()
116 u_register_t mpidr = read_mpidr_el1(); in imx_pwr_domain_off()
135 u_register_t mpidr = read_mpidr_el1(); in imx_domain_suspend()
211 u_register_t mpidr = read_mpidr_el1(); in imx_domain_suspend_finish()
/external/arm-trusted-firmware/plat/imx/imx8qx/
Dimx8qx_psci.c102 u_register_t mpidr = read_mpidr_el1(); in imx_pwr_domain_off()
113 u_register_t mpidr = read_mpidr_el1(); in imx_domain_suspend()
166 u_register_t mpidr = read_mpidr_el1(); in imx_domain_suspend_finish()
/external/arm-trusted-firmware/plat/imx/imx8m/imx8mq/
Dimx8mq_psci.c45 uint64_t mpidr = read_mpidr_el1(); in imx_domain_suspend()
71 uint64_t mpidr = read_mpidr_el1(); in imx_domain_suspend_finish()
/external/arm-trusted-firmware/plat/marvell/a3700/common/
Da3700_ea.c18 read_mpidr_el1()); in plat_ea_handler()
/external/arm-trusted-firmware/plat/arm/css/common/
Dcss_topology.c26 assert((read_mpidr_el1() & MPIDR_MT_MASK) != 0); in plat_core_pos_by_mpidr()
/external/arm-trusted-firmware/plat/hisilicon/hikey/
Dhikey_pm.c99 u_register_t mpidr = read_mpidr_el1(); in hikey_pwr_domain_suspend()
143 mpidr = read_mpidr_el1(); in hikey_pwr_domain_suspend_finish()
/external/arm-trusted-firmware/plat/common/aarch64/
Dplat_common.c79 read_mpidr_el1()); in plat_ea_handler()

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