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Searched refs:reg_base (Results 1 – 25 of 83) sorted by relevance

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/external/arm-trusted-firmware/drivers/rpi3/sdhost/
Drpi3_sdhost.c50 uintptr_t reg_base = rpi3_sdhost_params.reg_base; in rpi3_sdhost_waitcommand() local
54 while ((mmio_read_32(reg_base + HC_COMMAND) & HC_CMD_ENABLE) in rpi3_sdhost_waitcommand()
73 uintptr_t reg_base = rpi3_sdhost_params.reg_base; in send_command_raw() local
79 status = mmio_read_32(reg_base + HC_HOSTSTATUS); in send_command_raw()
81 mmio_write_32(reg_base + HC_HOSTSTATUS, status); in send_command_raw()
87 mmio_write_32(reg_base + HC_ARGUMENT, arg); in send_command_raw()
88 mmio_write_32(reg_base + HC_COMMAND, cmd | HC_CMD_ENABLE); in send_command_raw()
137 uintptr_t reg_base = rpi3_sdhost_params.reg_base; in rpi3_drain_fifo() local
142 while (mmio_read_32(reg_base + HC_HOSTSTATUS) & HC_HSTST_HAVEDATA) { in rpi3_drain_fifo()
143 mmio_read_32(reg_base + HC_DATAPORT); in rpi3_drain_fifo()
[all …]
/external/arm-trusted-firmware/drivers/imx/usdhc/
Dimx_usdhc.c44 uintptr_t reg_base = imx_usdhc_params.reg_base; in imx_usdhc_set_clk() local
58 mmio_clrbits32(reg_base + VENDSPEC, VENDSPEC_CARD_CLKEN); in imx_usdhc_set_clk()
59 mmio_clrsetbits32(reg_base + SYSCTRL, SYSCTRL_CLOCK_MASK, clk); in imx_usdhc_set_clk()
62 mmio_setbits32(reg_base + VENDSPEC, VENDSPEC_PER_CLKEN | VENDSPEC_CARD_CLKEN); in imx_usdhc_set_clk()
68 uintptr_t reg_base = imx_usdhc_params.reg_base; in imx_usdhc_initialize() local
70 assert((imx_usdhc_params.reg_base & MMC_BLOCK_MASK) == 0); in imx_usdhc_initialize()
73 mmio_setbits32(reg_base + SYSCTRL, SYSCTRL_RSTA); in imx_usdhc_initialize()
76 while ((mmio_read_32(reg_base + SYSCTRL) & SYSCTRL_RSTA)) { in imx_usdhc_initialize()
82 mmio_write_32(reg_base + MMCBOOT, 0); in imx_usdhc_initialize()
83 mmio_write_32(reg_base + MIXCTRL, 0); in imx_usdhc_initialize()
[all …]
/external/u-boot/drivers/spi/
Dcadence_qspi_apb.c167 #define CQSPI_GET_RD_SRAM_LEVEL(reg_base) \ argument
168 (((readl(reg_base + CQSPI_REG_SDRAMLEVEL)) >> \
171 #define CQSPI_GET_WR_SRAM_LEVEL(reg_base) \ argument
172 (((readl(reg_base + CQSPI_REG_SDRAMLEVEL)) >> \
188 void cadence_qspi_apb_controller_enable(void *reg_base) in cadence_qspi_apb_controller_enable() argument
191 reg = readl(reg_base + CQSPI_REG_CONFIG); in cadence_qspi_apb_controller_enable()
193 writel(reg, reg_base + CQSPI_REG_CONFIG); in cadence_qspi_apb_controller_enable()
196 void cadence_qspi_apb_controller_disable(void *reg_base) in cadence_qspi_apb_controller_disable() argument
199 reg = readl(reg_base + CQSPI_REG_CONFIG); in cadence_qspi_apb_controller_disable()
201 writel(reg, reg_base + CQSPI_REG_CONFIG); in cadence_qspi_apb_controller_disable()
[all …]
Dcadence_qspi.h72 void cadence_qspi_apb_chipselect(void *reg_base,
74 void cadence_qspi_apb_set_clk_mode(void *reg_base, uint mode);
75 void cadence_qspi_apb_config_baudrate_div(void *reg_base,
77 void cadence_qspi_apb_delay(void *reg_base,
81 void cadence_qspi_apb_enter_xip(void *reg_base, char xip_dummy);
82 void cadence_qspi_apb_readdata_capture(void *reg_base,
Datmel_spi.c242 struct at91_spi *reg_base = bus_plat->regs; in atmel_spi_claim_bus() local
262 writel(csrx, &reg_base->csr[cs]); in atmel_spi_claim_bus()
269 writel(mode, &reg_base->mr); in atmel_spi_claim_bus()
271 writel(ATMEL_SPI_CR_SPIEN, &reg_base->cr); in atmel_spi_claim_bus()
321 struct at91_spi *reg_base = bus_plat->regs; in atmel_spi_xfer() local
363 readl(&reg_base->rdr); in atmel_spi_xfer()
367 status = readl(&reg_base->sr); in atmel_spi_xfer()
377 writel(value, &reg_base->tdr); in atmel_spi_xfer()
382 value = readl(&reg_base->rdr); in atmel_spi_xfer()
395 wait_for_bit_le32(&reg_base->sr, in atmel_spi_xfer()
/external/arm-trusted-firmware/drivers/rpi3/gpio/
Drpi3_gpio.c46 uintptr_t reg_base = rpi3_gpio_params.reg_base; in rpi3_gpio_get_select() local
49 uintptr_t reg_sel = reg_base + RPI3_GPIO_GPFSEL(regN); in rpi3_gpio_get_select()
72 uintptr_t reg_base = rpi3_gpio_params.reg_base; in rpi3_gpio_set_select() local
75 uintptr_t reg_sel = reg_base + RPI3_GPIO_GPFSEL(regN); in rpi3_gpio_set_select()
109 uintptr_t reg_base = rpi3_gpio_params.reg_base; in rpi3_gpio_get_value() local
112 uintptr_t reg_lev = reg_base + RPI3_GPIO_GPLEV(regN); in rpi3_gpio_get_value()
122 uintptr_t reg_base = rpi3_gpio_params.reg_base; in rpi3_gpio_set_value() local
125 uintptr_t reg_set = reg_base + RPI3_GPIO_GPSET(regN); in rpi3_gpio_set_value()
126 uintptr_t reg_clr = reg_base + RPI3_GPIO_GPSET(regN); in rpi3_gpio_set_value()
140 uintptr_t reg_base = rpi3_gpio_params.reg_base; in rpi3_gpio_set_pull() local
[all …]
/external/u-boot/drivers/ata/
Dahci_sunxi.c17 static int sunxi_ahci_phy_init(u8 *reg_base) in sunxi_ahci_phy_init() argument
22 writel(0, reg_base + AHCI_RWCR); in sunxi_ahci_phy_init()
25 setbits_le32(reg_base + AHCI_PHYCS1R, 0x1 << 19); in sunxi_ahci_phy_init()
26 clrsetbits_le32(reg_base + AHCI_PHYCS0R, in sunxi_ahci_phy_init()
29 clrsetbits_le32(reg_base + AHCI_PHYCS1R, in sunxi_ahci_phy_init()
32 setbits_le32(reg_base + AHCI_PHYCS1R, (0x1 << 28) | (0x1 << 15)); in sunxi_ahci_phy_init()
33 clrbits_le32(reg_base + AHCI_PHYCS1R, (0x1 << 19)); in sunxi_ahci_phy_init()
34 clrsetbits_le32(reg_base + AHCI_PHYCS0R, (0x7 << 20), (0x3 << 20)); in sunxi_ahci_phy_init()
35 clrsetbits_le32(reg_base + AHCI_PHYCS2R, (0x1f << 5), (0x19 << 5)); in sunxi_ahci_phy_init()
38 setbits_le32(reg_base + AHCI_PHYCS0R, (0x1 << 19)); in sunxi_ahci_phy_init()
[all …]
/external/u-boot/drivers/net/pfe_eth/
Dpfe_mdio.c19 void *reg_base = bus->priv; in pfe_write_addr() local
30 writel(reg_data, reg_base + EMAC_MII_DATA_REG); in pfe_write_addr()
35 while (!(readl(reg_base + EMAC_IEVENT_REG) & EMAC_IEVENT_MII)) { in pfe_write_addr()
45 writel(EMAC_IEVENT_MII, reg_base + EMAC_IEVENT_REG); in pfe_write_addr()
53 void *reg_base = bus->priv; in pfe_phy_read() local
78 writel(reg_data, reg_base + EMAC_MII_DATA_REG); in pfe_phy_read()
83 while (!(readl(reg_base + EMAC_IEVENT_REG) & EMAC_IEVENT_MII)) { in pfe_phy_read()
93 writel(EMAC_IEVENT_MII, reg_base + EMAC_IEVENT_REG); in pfe_phy_read()
98 val = (u16)readl(reg_base + EMAC_MII_DATA_REG); in pfe_phy_read()
99 debug("%s: %p phy: 0x%x reg:0x%08x val:%#x\n", __func__, reg_base, in pfe_phy_read()
[all …]
/external/u-boot/arch/arm/mach-uniphier/clk/
Dpll-base-ld20.c32 int uniphier_ld20_sscpll_init(unsigned long reg_base, unsigned int freq, in uniphier_ld20_sscpll_init() argument
35 void __iomem *base = sc_base + reg_base; in uniphier_ld20_sscpll_init()
63 int uniphier_ld20_sscpll_ssc_en(unsigned long reg_base) in uniphier_ld20_sscpll_ssc_en() argument
65 void __iomem *base = sc_base + reg_base; in uniphier_ld20_sscpll_ssc_en()
75 int uniphier_ld20_sscpll_set_regi(unsigned long reg_base, unsigned regi) in uniphier_ld20_sscpll_set_regi() argument
77 void __iomem *base = sc_base + reg_base; in uniphier_ld20_sscpll_set_regi()
88 int uniphier_ld20_vpll27_init(unsigned long reg_base) in uniphier_ld20_vpll27_init() argument
90 void __iomem *base = sc_base + reg_base; in uniphier_ld20_vpll27_init()
108 int uniphier_ld20_dspll_init(unsigned long reg_base) in uniphier_ld20_dspll_init() argument
110 void __iomem *base = sc_base + reg_base; in uniphier_ld20_dspll_init()
Dpll.h14 int uniphier_ld20_sscpll_init(unsigned long reg_base, unsigned int freq,
16 int uniphier_ld20_sscpll_ssc_en(unsigned long reg_base);
17 int uniphier_ld20_sscpll_set_regi(unsigned long reg_base, unsigned regi);
18 int uniphier_ld20_vpll27_init(unsigned long reg_base);
19 int uniphier_ld20_dspll_init(unsigned long reg_base);
/external/u-boot/drivers/mmc/
Dkona_sdhci.c81 void *reg_base; in kona_sdhci_init() local
91 reg_base = (void *)CONFIG_SYS_SDIO_BASE0; in kona_sdhci_init()
92 ret = clk_sdio_enable(reg_base, CONFIG_SYS_SDIO0_MAX_CLK, in kona_sdhci_init()
96 reg_base = (void *)CONFIG_SYS_SDIO_BASE1; in kona_sdhci_init()
97 ret = clk_sdio_enable(reg_base, CONFIG_SYS_SDIO1_MAX_CLK, in kona_sdhci_init()
101 reg_base = (void *)CONFIG_SYS_SDIO_BASE2; in kona_sdhci_init()
102 ret = clk_sdio_enable(reg_base, CONFIG_SYS_SDIO2_MAX_CLK, in kona_sdhci_init()
106 reg_base = (void *)CONFIG_SYS_SDIO_BASE3; in kona_sdhci_init()
107 ret = clk_sdio_enable(reg_base, CONFIG_SYS_SDIO3_MAX_CLK, in kona_sdhci_init()
121 host->ioaddr = reg_base; in kona_sdhci_init()
/external/u-boot/drivers/usb/musb-new/
Dda8xx.c66 void __iomem *reg_base = musb->ctrl_base; in da8xx_musb_interrupt() local
79 status = musb_readl(reg_base, DA8XX_USB_INTR_SRC_MASKED_REG); in da8xx_musb_interrupt()
83 musb_writel(reg_base, DA8XX_USB_INTR_SRC_CLEAR_REG, status); in da8xx_musb_interrupt()
99 int drvvbus = musb_readl(reg_base, DA8XX_USB_STAT_REG); in da8xx_musb_interrupt()
143 musb_writel(reg_base, DA8XX_USB_END_OF_INTR_REG, 0); in da8xx_musb_interrupt()
153 void __iomem *reg_base = musb->ctrl_base; in da8xx_musb_init() local
174 musb_readb(reg_base, DA8XX_USB_CTRL_REG)); in da8xx_musb_init()
195 void __iomem *reg_base = musb->ctrl_base; in da8xx_musb_enable() local
202 musb_writel(reg_base, DA8XX_USB_INTR_MASK_SET_REG, mask); in da8xx_musb_enable()
205 musb_writel(reg_base, DA8XX_USB_INTR_SRC_SET_REG, in da8xx_musb_enable()
[all …]
Dam35x.c94 void __iomem *reg_base = musb->ctrl_base; in am35x_musb_enable() local
101 musb_writel(reg_base, EP_INTR_MASK_SET_REG, epmask); in am35x_musb_enable()
102 musb_writel(reg_base, CORE_INTR_MASK_SET_REG, AM35X_INTR_USB_MASK); in am35x_musb_enable()
106 musb_writel(reg_base, CORE_INTR_SRC_SET_REG, in am35x_musb_enable()
118 void __iomem *reg_base = musb->ctrl_base; in am35x_musb_disable() local
120 musb_writel(reg_base, CORE_INTR_MASK_CLEAR_REG, AM35X_INTR_USB_MASK); in am35x_musb_disable()
121 musb_writel(reg_base, EP_INTR_MASK_CLEAR_REG, in am35x_musb_disable()
124 musb_writel(reg_base, USB_END_OF_INTR_REG, 0); in am35x_musb_disable()
226 void __iomem *reg_base = musb->ctrl_base; in am35x_musb_interrupt() local
251 epintr = musb_readl(reg_base, EP_INTR_SRC_MASKED_REG); in am35x_musb_interrupt()
[all …]
Dmusb_dsps.c158 void __iomem *reg_base = musb->ctrl_base; in dsps_musb_enable() local
166 dsps_writel(reg_base, wrp->epintr_set, epmask); in dsps_musb_enable()
167 dsps_writel(reg_base, wrp->coreintr_set, coremask); in dsps_musb_enable()
171 dsps_writel(reg_base, wrp->coreintr_set, in dsps_musb_enable()
188 void __iomem *reg_base = musb->ctrl_base; in dsps_musb_disable() local
190 dsps_writel(reg_base, wrp->coreintr_clear, wrp->usb_bitmap); in dsps_musb_disable()
191 dsps_writel(reg_base, wrp->epintr_clear, in dsps_musb_disable()
194 dsps_writel(reg_base, wrp->eoi, 0); in dsps_musb_disable()
295 void __iomem *reg_base = musb->ctrl_base; in dsps_interrupt() local
311 epintr = dsps_readl(reg_base, wrp->epintr_status); in dsps_interrupt()
[all …]
/external/u-boot/drivers/pci_endpoint/
Dpcie-cadence.h230 void __iomem *reg_base; member
238 writeb(value, pcie->reg_base + reg); in cdns_pcie_writeb()
243 writew(value, pcie->reg_base + reg); in cdns_pcie_writew()
248 writel(value, pcie->reg_base + reg); in cdns_pcie_writel()
253 return readl(pcie->reg_base + reg); in cdns_pcie_readl()
260 writeb(value, pcie->reg_base + CDNS_PCIE_RP_BASE + reg); in cdns_pcie_rp_writeb()
266 writew(value, pcie->reg_base + CDNS_PCIE_RP_BASE + reg); in cdns_pcie_rp_writew()
272 writel(value, pcie->reg_base + CDNS_PCIE_RP_BASE + reg); in cdns_pcie_rp_writel()
279 writeb(value, pcie->reg_base + CDNS_PCIE_EP_FUNC_BASE(fn) + reg); in cdns_pcie_ep_fn_writeb()
285 writew(value, pcie->reg_base + CDNS_PCIE_EP_FUNC_BASE(fn) + reg); in cdns_pcie_ep_fn_writew()
[all …]
/external/arm-trusted-firmware/drivers/synopsys/emmc/
Ddw_mmc.c145 mmio_write_32(dw_params.reg_base + DWMMC_CMD, in dw_update_clk()
149 data = mmio_read_32(dw_params.reg_base + DWMMC_CMD); in dw_update_clk()
152 data = mmio_read_32(dw_params.reg_base + DWMMC_RINTSTS); in dw_update_clk()
173 data = mmio_read_32(dw_params.reg_base + DWMMC_STATUS); in dw_set_clk()
177 mmio_write_32(dw_params.reg_base + DWMMC_CLKENA, 0); in dw_set_clk()
180 mmio_write_32(dw_params.reg_base + DWMMC_CLKDIV, div); in dw_set_clk()
184 mmio_write_32(dw_params.reg_base + DWMMC_CLKENA, 1); in dw_set_clk()
185 mmio_write_32(dw_params.reg_base + DWMMC_CLKSRC, 0); in dw_set_clk()
194 assert((dw_params.reg_base & MMC_BLOCK_MASK) == 0); in dw_init()
196 base = dw_params.reg_base; in dw_init()
[all …]
/external/arm-trusted-firmware/plat/socionext/uniphier/
Duniphier_nand.c51 uintptr_t reg_base; member
87 mmio_write_32(nand->reg_base + DENALI_ECC_ENABLE, 0); in uniphier_nand_block_isbad()
89 mmio_write_32(nand->reg_base + DENALI_INTR_STATUS0, -1); in uniphier_nand_block_isbad()
102 status = mmio_read_32(nand->reg_base + DENALI_INTR_STATUS0); in uniphier_nand_block_isbad()
124 mmio_write_32(nand->reg_base + DENALI_ECC_ENABLE, 1); in uniphier_nand_read_pages()
125 mmio_write_32(nand->reg_base + DENALI_DMA_ENABLE, 1); in uniphier_nand_read_pages()
127 mmio_write_32(nand->reg_base + DENALI_INTR_STATUS0, -1); in uniphier_nand_read_pages()
147 status = mmio_read_32(nand->reg_base + DENALI_INTR_STATUS0); in uniphier_nand_read_pages()
150 mmio_write_32(nand->reg_base + DENALI_DMA_ENABLE, 0); in uniphier_nand_read_pages()
241 nand->reg_base = 0x68100000; in uniphier_nand_hw_init()
[all …]
/external/arm-trusted-firmware/drivers/marvell/comphy/
Dphy-comphy-3700.c610 uintptr_t reg_base = 0; in mvebu_a3700_comphy_usb3_power_on() local
625 reg_base = COMPHY_INDIRECT_REG; in mvebu_a3700_comphy_usb3_power_on()
629 reg_base = USB3_GBE1_PHY; in mvebu_a3700_comphy_usb3_power_on()
642 usb3_reg_set(reg_base, COMPHY_REG_LANE_CFG0_ADDR, PRD_TXDEEMPH0_MASK, in mvebu_a3700_comphy_usb3_power_on()
655 usb3_reg_set(reg_base, COMPHY_REG_LANE_CFG1_ADDR, data, mask, mode); in mvebu_a3700_comphy_usb3_power_on()
660 usb3_reg_set(reg_base, COMPHY_REG_LANE_CFG4_ADDR, in mvebu_a3700_comphy_usb3_power_on()
667 usb3_reg_set(reg_base, COMPHY_REG_TEST_MODE_CTRL_ADDR, in mvebu_a3700_comphy_usb3_power_on()
674 usb3_reg_set(reg_base, COMPHY_REG_GLOB_CLK_SRC_LO_ADDR, 0x0, in mvebu_a3700_comphy_usb3_power_on()
681 usb3_reg_set(reg_base, COMPHY_REG_GEN2_SET_2, in mvebu_a3700_comphy_usb3_power_on()
690 usb3_reg_set(reg_base, COMPHY_REG_GEN2_SET_3, in mvebu_a3700_comphy_usb3_power_on()
[all …]
/external/arm-trusted-firmware/drivers/ufs/
Dufs.c59 assert((ufs_params.reg_base != 0) && (val != NULL)); in ufshc_dme_get()
61 base = ufs_params.reg_base; in ufshc_dme_get()
94 assert((ufs_params.reg_base != 0)); in ufshc_dme_set()
96 base = ufs_params.reg_base; in ufshc_dme_set()
161 data = mmio_read_32(ufs_params.reg_base + UTRLDBR); in get_empty_slot()
221 mmio_write_32(ufs_params.reg_base + UTRLBA, in ufs_prepare_cmd()
223 mmio_write_32(ufs_params.reg_base + UTRLBAU, in ufs_prepare_cmd()
324 mmio_write_32(ufs_params.reg_base + UTRLBA, in ufs_prepare_query()
326 mmio_write_32(ufs_params.reg_base + UTRLBAU, in ufs_prepare_query()
377 mmio_write_32(ufs_params.reg_base + UTRLBA, in ufs_prepare_nop_out()
[all …]
/external/arm-trusted-firmware/plat/layerscape/common/
Dls_tzc380.c22 unsigned int reg_base; in tzc380_set_region() local
25 reg_base = (tzasc_base + TZASC_REGIONS_REG + (region_id << 4)); in tzc380_set_region()
28 reg = (reg_base + TZASC_REGION_ATTR_OFFSET); in tzc380_set_region()
31 reg = reg_base + TZASC_REGION_LOWADDR_OFFSET; in tzc380_set_region()
35 reg = reg_base + TZASC_REGION_HIGHADDR_OFFSET; in tzc380_set_region()
38 reg = reg_base + TZASC_REGION_ATTR_OFFSET; in tzc380_set_region()
/external/libffi/src/avr32/
Dffi.c72 char *reg_base = stack; in ffi_prep_args() local
82 *(void**)reg_base = ecif->rvalue; in ffi_prep_args()
111 addr = reg_base + (index * 4); in ffi_prep_args()
118 addr = reg_base + 4; in ffi_prep_args()
123 addr = reg_base + 12; in ffi_prep_args()
166 printf("r%d: 0x%08x\n", 12 - i, ((unsigned int*)reg_base)[i]); in ffi_prep_args()
275 register char *reg_base = stack; in ffi_prep_incoming_args_SYSV() local
290 *rvalue = *(void **)reg_base; in ffi_prep_incoming_args_SYSV()
320 *p_argv = (void*)reg_base + (index * 4); in ffi_prep_incoming_args_SYSV()
327 *p_argv = (void*)reg_base + 4; in ffi_prep_incoming_args_SYSV()
[all …]
/external/python/cpython2/Modules/_ctypes/libffi/src/avr32/
Dffi.c72 char *reg_base = stack; in ffi_prep_args() local
82 *(void**)reg_base = ecif->rvalue; in ffi_prep_args()
111 addr = reg_base + (index * 4); in ffi_prep_args()
118 addr = reg_base + 4; in ffi_prep_args()
123 addr = reg_base + 12; in ffi_prep_args()
166 printf("r%d: 0x%08x\n", 12 - i, ((unsigned int*)reg_base)[i]); in ffi_prep_args()
275 register char *reg_base = stack; in ffi_prep_incoming_args_SYSV() local
290 *rvalue = *(void **)reg_base; in ffi_prep_incoming_args_SYSV()
320 *p_argv = (void*)reg_base + (index * 4); in ffi_prep_incoming_args_SYSV()
327 *p_argv = (void*)reg_base + 4; in ffi_prep_incoming_args_SYSV()
[all …]
/external/arm-trusted-firmware/drivers/synopsys/ufs/
Ddw_ufs.c23 assert((params != NULL) && (params->reg_base != 0)); in dwufs_phy_init()
25 base = params->reg_base; in dwufs_phy_init()
103 assert((params != NULL) && (params->reg_base != 0)); in dwufs_phy_set_pwr_mode()
105 base = params->reg_base; in dwufs_phy_set_pwr_mode()
196 ufs_params.reg_base = params->reg_base; in dw_ufs_init()
/external/igt-gpu-tools/tests/i915/
Dgem_mocs_settings.c234 uint32_t reg_base) in create_read_batch() argument
240 batch[offset+1] = reg_base + (index * sizeof(uint32_t)); in create_read_batch()
260 uint32_t reg_base, in do_read_registers() argument
283 create_read_batch(reloc, batch, dst_handle, size, reg_base); in do_read_registers()
297 uint32_t reg_base) in create_write_batch() argument
305 batch[offset++] = reg_base + (i * 4); in create_write_batch()
316 uint32_t reg_base, in write_registers() argument
334 execbuf.batch_len = create_write_batch(batch, values, size, reg_base); in write_registers()
351 const uint32_t reg_base = get_engine_base(fd, engine); in check_control_registers() local
361 reg_base, in check_control_registers()
/external/u-boot/drivers/mailbox/
Dstm32-ipcc.c33 void __iomem *reg_base; member
110 ipcc->reg_base = (void __iomem *)addr; in stm32_ipcc_probe()
126 ipcc->reg_proc = ipcc->reg_base + ipcc->proc_id * IPCC_PROC_OFFST; in stm32_ipcc_probe()
137 ipcc->n_chans = readl(ipcc->reg_base + IPCC_HWCFGR); in stm32_ipcc_probe()

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