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Searched refs:reg_ctrl (Results 1 – 13 of 13) sorted by relevance

/external/OpenCSD/decoder/include/opencsd/etmv3/
Dtrc_cmp_cfg_etmv3.h143 return (bool)((m_cfg.reg_ctrl & CTRL_CYCLEACC) != 0); in isCycleAcc()
154 return (bool)((m_cfg.reg_ctrl & CTRL_DATAONLY) == 0); in isInstrTrace()
159 return (bool)((m_cfg.reg_ctrl & CTRL_DATAVAL) != 0); in isDataValTrace()
164 return (bool)((m_cfg.reg_ctrl & CTRL_DATAADDR) != 0); in isDataAddrTrace()
170 return (bool)((m_cfg.reg_ctrl & (CTRL_DATAADDR | CTRL_DATAVAL)) != 0); in isDataTrace()
205 return (bool)((m_cfg.reg_ctrl & CTRL_TS_ENA) != 0); in isTSEnabled()
211 return (bool)((m_cfg.reg_ctrl & CTRL_VMID_ENA) != 0); in isVMIDTrace()
Dtrc_pkt_types_etmv3.h164 uint32_t reg_ctrl; /**< Control Register */ member
/external/OpenCSD/decoder/include/opencsd/ptm/
Dtrc_cmp_cfg_ptm.h136 return (bool)((m_cfg.reg_ctrl & CTRL_BRANCH_BCAST) != 0); in enaBranchBCast()
141 return (bool)((m_cfg.reg_ctrl & CTRL_CYCLEACC) != 0); in enaCycleAcc()
146 return (bool)((m_cfg.reg_ctrl & CTRL_RETSTACK_ENA) != 0); in enaRetStack()
166 return (bool)((m_cfg.reg_ctrl & CTRL_TS_ENA) != 0); in enaTS()
188 return (bool)((m_cfg.reg_ctrl & CTRL_VMID_ENA) != 0); in enaVMID()
Dtrc_pkt_types_ptm.h124 uint32_t reg_ctrl; /**< Control Register */ member
/external/u-boot/drivers/spi/
Dmxc_spi.c153 s32 reg_ctrl, reg_config; in spi_cfg_mxc() local
165 reg_ctrl = MXC_CSPICTRL_MODE_MASK; in spi_cfg_mxc()
166 reg_write(&regs->ctrl, reg_ctrl); in spi_cfg_mxc()
167 reg_ctrl |= MXC_CSPICTRL_EN; in spi_cfg_mxc()
168 reg_write(&regs->ctrl, reg_ctrl); in spi_cfg_mxc()
188 reg_ctrl = (reg_ctrl & ~MXC_CSPICTRL_SELCHAN(3)) | in spi_cfg_mxc()
190 reg_ctrl = (reg_ctrl & ~MXC_CSPICTRL_PREDIV(0x0F)) | in spi_cfg_mxc()
192 reg_ctrl = (reg_ctrl & ~MXC_CSPICTRL_POSTDIV(0x0F)) | in spi_cfg_mxc()
221 debug("reg_ctrl = 0x%x\n", reg_ctrl); in spi_cfg_mxc()
222 reg_write(&regs->ctrl, reg_ctrl); in spi_cfg_mxc()
[all …]
/external/OpenCSD/decoder/source/ptm/
Dtrc_cmp_cfg_ptm.cpp44 m_cfg.reg_ctrl = 0; in PtmConfig()
55 return ctxtIdsizes[(m_cfg.reg_ctrl >> 14) & 0x3]; in CtxtIDBytes()
/external/OpenCSD/decoder/source/etmv3/
Dtrc_cmp_cfg_etmv3.cpp45 m_cfg.reg_ctrl = 0; in EtmV3Config()
62 return ctxtIdsizes[(m_cfg.reg_ctrl >> 14) & 0x3]; in CtxtIDBytes()
/external/OpenCSD/decoder/tests/snapshot_parser_lib/source/
Dss_to_dcdtree.cpp305 { ETMv3PTMRegCR, true, &cfg_regs.reg_ctrl, 0 }, in createETMv3Decoder()
343 { ETMv3PTMRegCR, true, &config.reg_ctrl, 0 }, in createPTMDecoder()
/external/OpenCSD/decoder/tests/source/
Dc_api_pkt_print_test.c672 trace_config_etmv3.reg_ctrl = 0x10001860; in create_decoder_etmv3()
697 trace_config_ptm.reg_ctrl = 0x10001000; in create_decoder_ptm()
/external/u-boot/arch/arm/include/asm/arch-sunxi/
Ddisplay.h139 u32 reg_ctrl; /* 0x870 */ member
/external/u-boot/arch/arm/mach-imx/mx6/
Dddr.c60 static void modify_dg_result(u32 *reg_st0, u32 *reg_st1, u32 *reg_ctrl) in modify_dg_result() argument
69 val_ctrl = readl(reg_ctrl); in modify_dg_result()
84 writel(val_ctrl, reg_ctrl); in modify_dg_result()
/external/u-boot/drivers/net/
De1000.c1722 uint32_t reg_ctrl, reg_ctrl_ext; in e1000_initialize_hardware_bits() local
1772 reg_ctrl = E1000_READ_REG(hw, CTRL); in e1000_initialize_hardware_bits()
1773 reg_ctrl &= ~(1 << 29); in e1000_initialize_hardware_bits()
1776 E1000_WRITE_REG(hw, CTRL, reg_ctrl); in e1000_initialize_hardware_bits()
/external/u-boot/drivers/video/sunxi/
Dsunxi_display.c520 setbits_le32(&de_be->reg_ctrl, SUNXI_DE_BE_REG_CTRL_LOAD_REGS); in sunxi_composer_enable()