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Searched refs:reg_mask (Results 1 – 11 of 11) sorted by relevance

/external/libffi/src/avr32/
Dffi.c75 unsigned int reg_mask = 0; in ffi_prep_args() local
83 reg_mask |= 1; in ffi_prep_args()
97 if(reg_mask != 0x1f) in ffi_prep_args()
108 while((reg_mask >> index) & 1) in ffi_prep_args()
112 reg_mask |= (1 << index); in ffi_prep_args()
116 if(!((reg_mask >> 1) & 1)) in ffi_prep_args()
119 reg_mask |= (3 << 1); in ffi_prep_args()
121 else if(!((reg_mask >> 3) & 1)) in ffi_prep_args()
124 reg_mask |= (3 << 3); in ffi_prep_args()
163 if((reg_mask & (1 << i)) == 0) in ffi_prep_args()
[all …]
/external/python/cpython2/Modules/_ctypes/libffi/src/avr32/
Dffi.c75 unsigned int reg_mask = 0; in ffi_prep_args() local
83 reg_mask |= 1; in ffi_prep_args()
97 if(reg_mask != 0x1f) in ffi_prep_args()
108 while((reg_mask >> index) & 1) in ffi_prep_args()
112 reg_mask |= (1 << index); in ffi_prep_args()
116 if(!((reg_mask >> 1) & 1)) in ffi_prep_args()
119 reg_mask |= (3 << 1); in ffi_prep_args()
121 else if(!((reg_mask >> 3) & 1)) in ffi_prep_args()
124 reg_mask |= (3 << 3); in ffi_prep_args()
163 if((reg_mask & (1 << i)) == 0) in ffi_prep_args()
[all …]
/external/u-boot/drivers/net/
Dmdio_mux_i2creg.c51 u32 reg_mask[2]; in mdio_mux_i2creg_probe() local
56 err = dev_read_u32_array(dev, "mux-reg-masks", reg_mask, 2); in mdio_mux_i2creg_probe()
87 priv->reg = (int)reg_mask[0]; in mdio_mux_i2creg_probe()
88 priv->mask = (int)reg_mask[1]; in mdio_mux_i2creg_probe()
/external/u-boot/drivers/pinctrl/mvebu/
Dpinctrl-armada-37xx.c68 u32 reg_mask; member
105 .reg_mask = _mask, \
115 .reg_mask = _mask, \
125 .reg_mask = _mask, \
135 .reg_mask = _mask, \
146 .reg_mask = _mask, \
272 unsigned int mask = grp->reg_mask; in armada_37xx_pmx_set_by_name()
/external/mesa3d/src/gallium/drivers/freedreno/a2xx/
Dir2_ra.c84 static unsigned reg_mask(struct ir2_context *ctx, unsigned idx) in reg_mask() function
157 if (reg_mask(ctx, idx) == 0) in ra_reg()
166 unsigned mask = reg_mask(ctx, idx); in ra_reg()
/external/u-boot/drivers/ddr/marvell/a38x/
Dddr3_training_ip_def.h157 unsigned int reg_mask; member
Dddr3_training_ip_flow.h78 u32 reg_addr, u32 data_value, u32 reg_mask);
Dddr3_init.h153 int ddr3_tip_reg_read(u32 dev_num, u32 reg_addr, u32 *data, u32 reg_mask);
Dddr3_training_leveling.c1692 u32 reg_val, reg_mask; in mv_ddr_rl_dqs_burst() local
1700 reg_mask = (TRAINING_ECC_MUX_MASK << TRAINING_ECC_MUX_OFFS) | in mv_ddr_rl_dqs_burst()
1702 reg_val &= ~reg_mask; in mv_ddr_rl_dqs_burst()
1709 reg_mask = (TRN_START_MASK << TRN_START_OFFS); in mv_ddr_rl_dqs_burst()
1710 reg_val &= ~reg_mask; in mv_ddr_rl_dqs_burst()
Dddr3_training.c1092 u32 data_value, u32 reg_mask) in ddr3_tip_bus_read_modify_write() argument
1110 data_value = (data_val & (~reg_mask)) | (data_value & reg_mask); in ddr3_tip_bus_read_modify_write()
1970 odpg_default_value[index_cnt].reg_mask)); in ddr3_tip_restore_dunit_regs()
/external/vixl/src/aarch64/
Dsimulator-aarch64.cc351 uint64_t reg_mask = (reg_size == kWRegSize) ? kWRegMask : kXRegMask; in AddWithCarry() local
354 left &= reg_mask; in AddWithCarry()
355 right &= reg_mask; in AddWithCarry()
356 uint64_t result = (left + right + carry_in) & reg_mask; in AddWithCarry()
2883 int64_t reg_mask = instr->GetSixtyFourBits() ? kXRegMask : kWRegMask; in VisitBitfield() local
2890 mask = (static_cast<unsigned>(diff) < (reg_size - 1)) ? mask : reg_mask; in VisitBitfield()