Home
last modified time | relevance | path

Searched refs:reg_read (Results 1 – 25 of 32) sorted by relevance

12

/external/u-boot/drivers/ddr/marvell/axp/
Dddr3_dfs.c74 reg = reg_read(REG_SDRAM_OPERATION_ADDR) & in wait_refresh_op_complete()
132 reg = reg_read(REG_DFS_ADDR); in ddr3_dfs_high_2_low()
141 reg = reg_read(REG_METAL_MASK_ADDR); in ddr3_dfs_high_2_low()
148 reg = reg_read(REG_DFS_ADDR); in ddr3_dfs_high_2_low()
182 reg = reg_read(REG_SDRAM_OPERATION_ADDR) & in ddr3_dfs_high_2_low()
187 reg = reg_read(REG_REGISTERED_DRAM_CTRL_ADDR); in ddr3_dfs_high_2_low()
197 reg = reg_read(REG_DDR3_MR1_CS_ADDR + in ddr3_dfs_high_2_low()
206 reg = reg_read(REG_DFS_ADDR); in ddr3_dfs_high_2_low()
212 reg = ((reg_read(REG_DFS_ADDR)) & (1 << REG_DFS_ATSR_OFFS)); in ddr3_dfs_high_2_low()
219 reg = reg_read(CPU_PLL_CLOCK_DIVIDER_CNTRL0); in ddr3_dfs_high_2_low()
[all …]
Dddr3_write_leveling.c75 reg = reg_read(REG_DUNIT_CTRL_LOW_ADDR); in ddr3_write_leveling_hw()
89 reg = reg_read(REG_DRAM_TRAINING_SHADOW_ADDR) | in ddr3_write_leveling_hw()
95 reg = reg_read(REG_DRAM_TRAINING_SHADOW_ADDR) & in ddr3_write_leveling_hw()
99 reg = reg_read(REG_DRAM_TRAINING_ADDR); in ddr3_write_leveling_hw()
162 reg = reg_read(REG_DUNIT_CTRL_LOW_ADDR) | in ddr3_write_leveling_hw()
218 reg = reg_read(REG_DRAM_TRAINING_2_ADDR) | in ddr3_wl_supplement()
251 (reg_read(REG_DRAM_TRAINING_2_ADDR) in ddr3_wl_supplement()
400 (reg_read(REG_DRAM_TRAINING_2_ADDR) in ddr3_wl_supplement()
450 reg = reg_read(REG_DRAM_TRAINING_2_ADDR); in ddr3_wl_supplement()
455 reg = reg_read(REG_DRAM_TRAINING_1_ADDR) | in ddr3_wl_supplement()
[all …]
Dddr3_init.c71 printf("0x%08x = 0x%08x\n", reg, reg_read(reg)); in debug_print_reg()
226 win_backup[ui] = reg_read(win_ctrl_reg + 0x4 * ui); in ddr3_save_and_set_training_windows()
377 soc_num = (reg_read(REG_SAMPLE_RESET_HIGH_ADDR) & SAR1_CPU_CORE_MASK) >> in ddr3_init_main()
394 reg = (reg_read(REG_DDRPHY_APLL_CTRL_ADDR) & ~(1 << 25)); in ddr3_init_main()
452 if (reg_read(REG_BOOTROM_ROUTINE_ADDR) & in ddr3_init_main()
473 reg = reg_read(REG_SDRAM_CONFIG_ADDR); in ddr3_init_main()
495 reg = reg_read(REG_SDRAM_CONFIG_ADDR); in ddr3_init_main()
512 reg = reg_read(REG_TRAINING_DEBUG_3_ADDR); in ddr3_init_main()
538 if ((ddr_width == 64) && (reg_read(REG_DDR_IO_ADDR) & in ddr3_init_main()
571 reg = reg_read(REG_STATIC_DRAM_DLB_CONTROL); in ddr3_init_main()
[all …]
Dddr3_hw_training.c105 reg = reg_read(REG_SDRAM_CONFIG_ADDR); in ddr3_hw_training()
114 reg = reg_read(REG_SDRAM_CONFIG_ADDR); in ddr3_hw_training()
123 reg = reg_read(REG_DUNIT_CTRL_LOW_ADDR); in ddr3_hw_training()
129 reg = reg_read(REG_DDR3_MR0_ADDR) >> 2; in ddr3_hw_training()
131 reg = reg_read(REG_DDR3_MR0_CS_ADDR) >> 2; in ddr3_hw_training()
139 reg = reg_read(REG_DDR3_MR2_ADDR) >> REG_DDR3_MR2_CWL_OFFS; in ddr3_hw_training()
141 reg = reg_read(REG_DDR3_MR2_CS_ADDR) >> REG_DDR3_MR2_CWL_OFFS; in ddr3_hw_training()
170 if (reg_read(REG_DDR_IO_ADDR) & (1 << REG_DDR_IO_CLK_RATIO_OFFS)) in ddr3_hw_training()
518 reg = reg_read(REG_SDRAM_TIMING_HIGH_ADDR); in ddr3_set_performance_params()
567 reg = reg_read(REG_PHY_REGISTRY_FILE_ACCESS_ADDR) & in ddr3_write_pup_reg()
[all …]
Dddr3_read_leveling.c78 reg = reg_read(REG_DRAM_TRAINING_SHADOW_ADDR) | in ddr3_read_leveling_hw()
84 reg = reg_read(REG_DRAM_TRAINING_SHADOW_ADDR) & in ddr3_read_leveling_hw()
89 if (reg_read(REG_DRAM_TRAINING_SHADOW_ADDR) & in ddr3_read_leveling_hw()
151 reg_read(REG_READ_DATA_READY_DELAYS_ADDR) & in ddr3_read_leveling_hw()
154 reg_read(REG_READ_DATA_SAMPLE_DELAYS_ADDR) & in ddr3_read_leveling_hw()
188 reg = reg_read(REG_DRAM_TRAINING_2_ADDR) | in ddr3_read_leveling_sw()
207 reg = reg_read(REG_DRAM_TRAINING_2_ADDR) & in ddr3_read_leveling_sw()
219 reg = reg_read(REG_READ_DATA_SAMPLE_DELAYS_ADDR); in ddr3_read_leveling_sw()
227 reg = reg_read(REG_READ_DATA_READY_DELAYS_ADDR); in ddr3_read_leveling_sw()
298 reg = reg_read(REG_DRAM_TRAINING_2_ADDR) | in ddr3_read_leveling_sw()
[all …]
Dxor.c27 xor_regs_ctrl_backup = reg_read(XOR_WINDOW_CTRL_REG(0, 0)); in mv_sys_xor_init()
29 xor_regs_base_backup[ui] = reg_read(XOR_BASE_ADDR_REG(0, ui)); in mv_sys_xor_init()
31 xor_regs_mask_backup[ui] = reg_read(XOR_SIZE_MASK_REG(0, ui)); in mv_sys_xor_init()
145 val = reg_read(XOR_CONFIG_REG(XOR_UNIT(chan), XOR_CHAN(chan))) in mv_xor_ctrl_set()
171 tmp = reg_read(XOR_CONFIG_REG(XOR_UNIT(chan), XOR_CHAN(chan))); in mv_xor_mem_init()
261 tmp = reg_read(XOR_CONFIG_REG(XOR_UNIT(chan), XOR_CHAN(chan))); in mv_xor_transfer()
351 state = reg_read(XOR_ACTIVATION_REG(XOR_UNIT(chan), XOR_CHAN(chan))); in mv_xor_state_get()
Dddr3_pbs.c108 reg = reg_read(REG_DRAM_TRAINING_2_ADDR) | in ddr3_pbs_tx()
159 reg = reg_read(REG_DRAM_TRAINING_2_ADDR) & in ddr3_pbs_tx()
285 reg = reg_read(REG_DRAM_TRAINING_2_ADDR) & in ddr3_pbs_tx()
381 reg = reg_read(REG_DRAM_TRAINING_2_ADDR); in ddr3_pbs_tx()
386 reg = reg_read(REG_DRAM_TRAINING_1_ADDR) | in ddr3_pbs_tx()
551 reg = reg_read(REG_DRAM_TRAINING_2_ADDR) | in ddr3_pbs_rx()
601 reg = reg_read(REG_DRAM_TRAINING_2_ADDR) & in ddr3_pbs_rx()
673 reg = reg_read(REG_DRAM_TRAINING_ADDR); in ddr3_pbs_rx()
679 reg = reg_read(REG_DRAM_TRAINING_2_ADDR); in ddr3_pbs_rx()
687 reg = (reg_read(REG_DRAM_TRAINING_2_ADDR)) in ddr3_pbs_rx()
[all …]
Dddr3_spd.c690 if (reg_read(REG_DDR_IO_ADDR) & (1 << REG_DDR_IO_CLK_RATIO_OFFS))
697 reg = (reg_read(REG_DDR3_MR0_ADDR) >> 2);
890 reg |= (reg_read(REG_SDRAM_ADDRESS_CTRL_ADDR) & 0xF0FFFF);
963 if (reg_read(REG_DDR_IO_ADDR) & (1 << REG_DDR_IO_CLK_RATIO_OFFS))
997 reg = reg_read(REG_DRAM_MAIN_PADS_CAL_ADDR);
1004 reg = reg_read(REG_DRAM_MAIN_PADS_CAL_ADDR);
1083 if (reg_read(REG_DDR_IO_ADDR) & (1 << REG_DDR_IO_CLK_RATIO_OFFS))
1197 reg = reg_read(REG_REGISTERED_DRAM_CTRL_ADDR);
1206 reg = (reg_read(REG_SDRAM_INIT_CTRL_ADDR)) &
1230 reg = reg_read(REG_SDRAM_OPERATION_ADDR) &
Dddr3_dqs.c138 reg = reg_read(REG_DRAM_TRAINING_2_ADDR) | in ddr3_dqs_centralization_rx()
158 reg = reg_read(REG_DRAM_TRAINING_2_ADDR) & in ddr3_dqs_centralization_rx()
187 reg = reg_read(REG_DRAM_TRAINING_2_ADDR) & in ddr3_dqs_centralization_rx()
193 reg = reg_read(REG_DRAM_TRAINING_2_ADDR); in ddr3_dqs_centralization_rx()
198 reg = reg_read(REG_DRAM_TRAINING_1_ADDR) | in ddr3_dqs_centralization_rx()
220 reg = reg_read(REG_DRAM_TRAINING_2_ADDR) | in ddr3_dqs_centralization_tx()
238 reg = reg_read(REG_DRAM_TRAINING_2_ADDR) & in ddr3_dqs_centralization_tx()
267 reg = reg_read(REG_DRAM_TRAINING_2_ADDR) & in ddr3_dqs_centralization_tx()
273 reg = reg_read(REG_DRAM_TRAINING_2_ADDR); in ddr3_dqs_centralization_tx()
278 reg = reg_read(REG_DRAM_TRAINING_1_ADDR) | in ddr3_dqs_centralization_tx()
Dddr3_sdram.c53 while (!(reg_read(XOR_CAUSE_REG(XOR_UNIT(chan))) & in xor_waiton_eng()
564 reg = reg_read(REG_SAMPLE_RESET_LOW_ADDR) & in ddr3_flush_l1_line()
641 reg = reg_read(REG_DRAM_TRAINING_ADDR); in ddr3_reset_phy_read_fifo()
648 reg = reg_read(REG_DRAM_TRAINING_2_ADDR); in ddr3_reset_phy_read_fifo()
657 reg = reg_read(REG_DRAM_TRAINING_2_ADDR) & in ddr3_reset_phy_read_fifo()
661 reg = reg_read(REG_DRAM_TRAINING_ADDR); in ddr3_reset_phy_read_fifo()
Dddr3_init.h127 static inline u32 reg_read(u32 addr) in reg_read() function
/external/u-boot/arch/arm/mach-mvebu/serdes/axp/
Dhigh_speed_env_lib.c142 if ((reg_read(GPP_DATA_IN_REG(2)) & MV_GPP66) == 0x0) in board_modules_scan()
174 sar = reg_read(MPP_SAMPLE_AT_RESET(0)); in board_cpu_freq_get()
175 sar_msb = reg_read(MPP_SAMPLE_AT_RESET(1)); in board_cpu_freq_get()
284 if (reg_read(REG_BOOTROM_ROUTINE_ADDR) & in serdes_phy_config()
304 cpu_avs = reg_read(CPU_AVS_CONTROL2_REG); in serdes_phy_config()
311 tmp2 = reg_read(CPU_AVS_CONTROL0_REG); in serdes_phy_config()
319 fabric_freq = (reg_read(MPP_SAMPLE_AT_RESET(0)) & in serdes_phy_config()
324 core_avs = reg_read(CORE_AVS_CONTROL_0REG); in serdes_phy_config()
336 core_avs = reg_read(CORE_AVS_CONTROL_2REG); in serdes_phy_config()
342 tmp2 = reg_read(GENERAL_PURPOSE_RESERVED0_REG); in serdes_phy_config()
[all …]
/external/u-boot/arch/arm/mach-mvebu/serdes/a38x/
Dctrl_pex.c44 tmp = reg_read(PEX_CAPABILITIES_REG(pex_idx)); in hws_pex_config()
50 tmp = reg_read(SOC_CTRL_REG); in hws_pex_config()
112 tmp = reg_read(PEX_DBG_STATUS_REG(pex_idx)); in hws_pex_config()
123 temp_pex_reg = reg_read((PEX_CFG_DIRECT_ACCESS in hws_pex_config()
129 temp_reg = (reg_read(PEX_CFG_DIRECT_ACCESS( in hws_pex_config()
171 tmp = reg_read(PEX_LINK_CTRL_STATUS2_REG(pex_idx)); in hws_pex_config()
179 tmp = reg_read(PEX_CTRL_REG(pex_idx)); in hws_pex_config()
215 dev_id = reg_read(PEX_CFG_DIRECT_ACCESS in hws_pex_config()
239 pex_status = reg_read(PEX_STATUS_REG(pex_if)); in pex_local_bus_num_set()
254 pex_status = reg_read(PEX_STATUS_REG(pex_if)); in pex_local_dev_num_set()
[all …]
Dsys_env_lib.c60 value = (reg_read(DEVICE_SAMPLE_AT_RESET1_REG) >> 15) & 0x1; in mv_board_tclk_get()
121 reg = reg_read(MPP_CONTROL_REG(MPP_REG_NUM(gpio))); in sys_env_suspend_wakeup_check()
127 reg = reg_read(GPP_DATA_OUT_EN_REG(GPP_REG_NUM(gpio))); in sys_env_suspend_wakeup_check()
135 reg = reg_read(GPP_DATA_IN_REG(GPP_REG_NUM(gpio))); in sys_env_suspend_wakeup_check()
191 u32 default_ctrl_id, ctrl_id = reg_read(DEV_ID_REG); in sys_env_model_get()
229 g_dev_id = reg_read(DEVICE_SAMPLE_AT_RESET1_REG); in sys_env_device_id_get()
256 value = reg_read(DEV_VERSION_ID_REG); in sys_env_device_rev_get()
270 sar_freq = reg_read(DEVICE_SAMPLE_AT_RESET1_REG); in mv_avs_init()
277 u32 avs_reg_data = reg_read(AVS_ENABLED_CONTROL); in mv_avs_init()
Dhigh_speed_env_spec.c1405 data = reg_read(CORE_PLL_CONFIG_REG); in hws_pre_serdes_init_config()
1463 data = reg_read(reg_addr); in serdes_polarity_config()
1568 reg_data = reg_read(GENERAL_PURPOSE_RESERVED0_REG); in serdes_pex_usb3_pipe_delay_w_a()
1614 reg_satr1 = reg_read(DEVICE_SAMPLE_AT_RESET1_REG); in hws_serdes_pex_ref_clock_satr_get()
1724 reg_data = reg_read(SOC_CONTROL_REG1); in serdes_power_up_ctrl()
1732 reg_read(((PEX_IF_REGS_BASE(pex_idx)) + in serdes_power_up_ctrl()
1743 reg_read(((PEX_IF_REGS_BASE(pex_idx)) + in serdes_power_up_ctrl()
1751 reg_read(((PEX_IF_REGS_BASE(pex_idx)) + in serdes_power_up_ctrl()
1863 reg_data = reg_read(GBE_CONFIGURATION_REG); in serdes_power_up_ctrl()
2114 reg_data = reg_read(POWER_AND_PLL_CTRL_REG + in hws_ref_clock_set()
[all …]
Dseq_exec.c54 reg_data = reg_read(reg_addr); in write_op_execute()
113 reg_data = reg_read(reg_addr) & mask; in poll_op_execute()
/external/u-boot/arch/arm/mach-mvebu/
Ddram.c123 xor_ctrl_save = reg_read(XOR_WINDOW_CTRL_REG(SCRB_XOR_UNIT, in mv_xor_init2()
125 xor_base_save = reg_read(XOR_BASE_ADDR_REG(SCRB_XOR_UNIT, in mv_xor_init2()
127 xor_mask_save = reg_read(XOR_SIZE_MASK_REG(SCRB_XOR_UNIT, in mv_xor_init2()
178 temp = reg_read(REG_SDRAM_CONFIG_ADDR); in dram_ecc_scrubbing()
208 temp = reg_read(REG_SDRAM_CONFIG_ADDR); in dram_ecc_scrubbing()
215 if (reg_read(REG_SDRAM_CONFIG_ADDR) & (1 << REG_SDRAM_CONFIG_ECC_OFFS)) in ecc_enabled()
226 if (reg_read(REG_SDRAM_CONFIG_ADDR) & (1 << REG_SDRAM_CONFIG_WIDTH_OFFS)) in bus_width()
244 int val = reg_read(REG_DUNIT_CTRL_LOW_ADDR); in cycle_mode()
/external/u-boot/drivers/ddr/marvell/a38x/
Dmv_ddr_plat.c195 if ((reg_read(TSEN_CONTROL_MSB_REG) & TSEN_CONTROL_MSB_RST_MASK) == 0) { in ddr3_ctrl_get_junc_temp()
198 reg = reg_read(TSEN_CONTROL_LSB_REG); in ddr3_ctrl_get_junc_temp()
206 if ((reg_read(TSEN_STATUS_REG) & TSEN_STATUS_READOUT_VALID_MASK) == 0) { in ddr3_ctrl_get_junc_temp()
211 reg = reg_read(TSEN_STATUS_REG); in ddr3_ctrl_get_junc_temp()
243 *data = reg_read(addr) & mask; in dunit_read()
368 reg = reg_read(DUAL_DUNIT_CFG_REG); in ddr3_tip_a38x_select_ddr_controller()
393 reg = (reg_read(REG_DEVICE_SAR1_ADDR) >> in mv_ddr_sar_freq_get()
397 ref_clk_satr = reg_read(DEVICE_SAMPLE_AT_RESET2_REG); in mv_ddr_sar_freq_get()
487 reg = (reg_read(REG_DEVICE_SAR1_ADDR) >> in ddr3_tip_a38x_get_medium_freq()
491 ref_clk_satr = reg_read(DEVICE_SAMPLE_AT_RESET2_REG); in ddr3_tip_a38x_get_medium_freq()
[all …]
Dmv_ddr_sys_env_lib.c68 reg = reg_read(MPP_CONTROL_REG(MPP_REG_NUM(gpio))); in mv_ddr_sys_env_suspend_wakeup_check()
74 reg = reg_read(GPP_DATA_OUT_EN_REG(GPP_REG_NUM(gpio))); in mv_ddr_sys_env_suspend_wakeup_check()
82 reg = reg_read(GPP_DATA_IN_REG(GPP_REG_NUM(gpio))); in mv_ddr_sys_env_suspend_wakeup_check()
97 return reg_read(DDR3_RANK_CTRL_REG) & in mv_ddr_sys_env_get_cs_ena_from_reg()
Dxor.c26 ui_xor_regs_ctrl_backup = reg_read(XOR_WINDOW_CTRL_REG(0, 0)); in mv_sys_xor_init()
29 reg_read(XOR_BASE_ADDR_REG(0, ui)); in mv_sys_xor_init()
32 reg_read(XOR_SIZE_MASK_REG(0, ui)); in mv_sys_xor_init()
156 old_value = reg_read(XOR_CONFIG_REG(XOR_UNIT(chan), XOR_CHAN(chan))) & in mv_xor_ctrl_set()
185 temp = reg_read(XOR_CONFIG_REG(XOR_UNIT(chan), XOR_CHAN(chan))); in mv_xor_mem_init()
253 state = reg_read(XOR_ACTIVATION_REG(XOR_UNIT(chan), XOR_CHAN(chan))); in mv_xor_state_get()
417 temp = reg_read(XOR_CONFIG_REG(XOR_UNIT(chan), XOR_CHAN(chan))); in mv_xor_transfer()
Dddr_ml_wrapper.h133 static inline u32 reg_read(u32 addr) in reg_read() function
/external/igt-gpu-tools/tests/i915/
Dgem_reg_read.c51 struct local_drm_i915_reg_read reg_read; in read_register() local
52 reg_read.offset = offset; in read_register()
54 if (drmIoctl(fd, REG_READ_IOCTL, &reg_read)) in read_register()
57 *val = reg_read.val; in read_register()
/external/u-boot/drivers/spi/
Dmxc_spi.c34 #define reg_read readl macro
206 reg_config = reg_read(&regs->cfg); in spi_cfg_mxc()
307 status = reg_read(&regs->stat); in spi_xchg_single()
314 status = reg_read(&regs->stat); in spi_xchg_single()
325 data = reg_read(&regs->rxdata); in spi_xchg_single()
338 tmp = reg_read(&regs->rxdata); in spi_xchg_single()
/external/u-boot/board/Synology/ds414/
Dds414.c166 pwr_mng_ctrl_reg = reg_read(POWER_MNG_CTRL_REG); in board_init()
Dcmd_syno.c156 u32 pwr_mng_ctrl_reg = reg_read(POWER_MNG_CTRL_REG); in do_syno_clk_gate()

12