/external/v8/src/codegen/arm64/ |
D | assembler-arm64-inl.h | 915 Instr Assembler::ImmS(unsigned imms, unsigned reg_size) { 916 DCHECK(((reg_size == kXRegSizeInBits) && is_uint6(imms)) || 917 ((reg_size == kWRegSizeInBits) && is_uint5(imms))); 918 USE(reg_size); 922 Instr Assembler::ImmR(unsigned immr, unsigned reg_size) { 923 DCHECK(((reg_size == kXRegSizeInBits) && is_uint6(immr)) || 924 ((reg_size == kWRegSizeInBits) && is_uint5(immr))); 925 USE(reg_size); 930 Instr Assembler::ImmSetBits(unsigned imms, unsigned reg_size) { 931 DCHECK((reg_size == kWRegSizeInBits) || (reg_size == kXRegSizeInBits)); [all …]
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D | instructions-arm64.cc | 79 static uint64_t RepeatBitsAcrossReg(unsigned reg_size, uint64_t value, in RepeatBitsAcrossReg() argument 83 DCHECK((reg_size == kWRegSizeInBits) || (reg_size == kXRegSizeInBits)); in RepeatBitsAcrossReg() 85 for (unsigned i = width; i < reg_size; i *= 2) { in RepeatBitsAcrossReg() 95 unsigned reg_size = SixtyFourBits() ? kXRegSizeInBits : kWRegSizeInBits; in ImmLogical() local 135 reg_size, RotateRight(bits, imm_r & mask, width), width); in ImmLogical()
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D | macro-assembler-arm64.cc | 104 unsigned reg_size = rd.SizeInBits(); in LogicalMacro() local 159 if (IsImmLogical(immediate, reg_size, &n, &imm_s, &imm_r)) { in LogicalMacro() 225 unsigned reg_size = rd.SizeInBits(); in Mov() local 236 if (CountClearHalfWords(~imm, reg_size) > in Mov() 237 CountClearHalfWords(imm, reg_size)) { in Mov() 249 DCHECK_EQ(reg_size % 16, 0); in Mov() 540 unsigned TurboAssembler::CountClearHalfWords(uint64_t imm, unsigned reg_size) { in CountClearHalfWords() argument 541 DCHECK_EQ(reg_size % 8, 0); in CountClearHalfWords() 543 for (unsigned i = 0; i < (reg_size / 16); i++) { in CountClearHalfWords() 554 bool TurboAssembler::IsImmMovz(uint64_t imm, unsigned reg_size) { in IsImmMovz() argument [all …]
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/external/mesa3d/src/gallium/drivers/iris/ |
D | iris_perf.c | 60 uint32_t reg, uint32_t reg_size, in iris_perf_store_register_mem() argument 65 if (reg_size == 8) { in iris_perf_store_register_mem() 68 assert(reg_size == 4); in iris_perf_store_register_mem() 79 uint32_t reg, uint32_t reg_size,
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/external/jemalloc_new/src/ |
D | bin.c | 8 #define BIN_INFO_bin_yes(reg_size, slab_size, nregs) \ argument 9 {reg_size, slab_size, nregs, BITMAP_INFO_INITIALIZER(nregs)}, 10 #define BIN_INFO_bin_no(reg_size, slab_size, nregs) argument
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D | android_je_mallinfo.c | 41 total_bytes += bin_infos[j].reg_size * bin->stats.curregs; in accumulate_small_allocs() 107 mi.ordblks = bin_infos[bidx].reg_size * bin->stats.curregs; in je_mallinfo_bin_info()
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/external/mesa3d/src/intel/compiler/ |
D | brw_fs_reg_allocate.cpp | 878 const unsigned reg_size = dst.component_size(bld.dispatch_width()) / in emit_unspill() local 880 assert(count % reg_size == 0); in emit_unspill() 882 for (unsigned i = 0; i < count / reg_size; i++) { in emit_unspill() 897 unspill_inst->size_written = reg_size * REG_SIZE; in emit_unspill() 903 BRW_DATAPORT_OWORD_BLOCK_DWORDS(reg_size * 8), in emit_unspill() 924 dst.offset += reg_size * REG_SIZE; in emit_unspill() 925 spill_offset += reg_size * REG_SIZE; in emit_unspill() 934 const unsigned reg_size = src.component_size(bld.dispatch_width()) / in emit_spill() local 936 assert(count % reg_size == 0); in emit_spill() 938 for (unsigned i = 0; i < count / reg_size; i++) { in emit_spill() [all …]
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D | brw_ir_vec4.h | 433 const unsigned reg_size = in regs_read() local 435 return DIV_ROUND_UP(reg_offset(inst->src[i]) % reg_size + inst->size_read(i), in regs_read() 436 reg_size); in regs_read()
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/external/jemalloc_new/test/unit/ |
D | slab.c | 17 (bin_info->reg_size * regind)); in TEST_BEGIN() 21 bin_info->reg_size); in TEST_BEGIN()
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D | junk.c | 22 for (i = 0; i < bin_info->reg_size; i++) { in arena_dalloc_junk_small_intercept() 25 i, bin_info->reg_size); in arena_dalloc_junk_small_intercept()
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/external/jemalloc/src/ |
D | android_je_mallinfo.c | 37 mi.uordblks += arena_bin_info[j].reg_size * bin->stats.curregs; in je_mallinfo() 73 mi.fsmblks += arena_bin_info[j].reg_size * bin->stats.curregs; in __mallinfo_arena_info() 92 mi.ordblks = arena_bin_info[bidx].reg_size * bin->stats.curregs; in __mallinfo_bin_info()
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D | stats.c | 69 size_t reg_size, run_size, curregs; in stats_arena_bins_print() local 85 CTL_M2_GET("arenas.bin.0.size", j, ®_size, size_t); in stats_arena_bins_print() 159 reg_size, j, curregs * reg_size, nmalloc, in stats_arena_bins_print() 169 reg_size, j, curregs * reg_size, nmalloc, in stats_arena_bins_print()
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/external/vixl/src/aarch64/ |
D | instructions-aarch64.cc | 33 static uint64_t RepeatBitsAcrossReg(unsigned reg_size, in RepeatBitsAcrossReg() argument 38 VIXL_ASSERT((reg_size == kWRegSize) || (reg_size == kXRegSize)); in RepeatBitsAcrossReg() 40 for (unsigned i = width; i < reg_size; i *= 2) { in RepeatBitsAcrossReg() 110 unsigned reg_size = GetSixtyFourBits() ? kXRegSize : kWRegSize; in GetImmLogical() local 149 return RepeatBitsAcrossReg(reg_size, in GetImmLogical()
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D | simulator-aarch64.cc | 342 uint64_t Simulator::AddWithCarry(unsigned reg_size, in AddWithCarry() argument 348 VIXL_ASSERT((reg_size == kXRegSize) || (reg_size == kWRegSize)); in AddWithCarry() 350 uint64_t max_uint = (reg_size == kWRegSize) ? kWMaxUInt : kXMaxUInt; in AddWithCarry() 351 uint64_t reg_mask = (reg_size == kWRegSize) ? kWRegMask : kXRegMask; in AddWithCarry() 352 uint64_t sign_mask = (reg_size == kWRegSize) ? kWSignMask : kXSignMask; in AddWithCarry() 359 ReadNzcv().SetN(CalcNFlag(result, reg_size)); in AddWithCarry() 381 int64_t Simulator::ShiftOperand(unsigned reg_size, in ShiftOperand() argument 385 VIXL_ASSERT((reg_size == kWRegSize) || (reg_size == kXRegSize)); in ShiftOperand() 392 if (reg_size == kXRegSize) { in ShiftOperand() 408 uvalue |= ~UINT64_C(0) << (reg_size - amount); in ShiftOperand() [all …]
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D | macro-assembler-aarch64.cc | 444 unsigned reg_size = rd.GetSizeInBits(); in MoveImmediateHelper() local 455 if (CountClearHalfWords(~imm, reg_size) > in MoveImmediateHelper() 456 CountClearHalfWords(imm, reg_size)) { in MoveImmediateHelper() 472 VIXL_ASSERT((reg_size % 16) == 0); in MoveImmediateHelper() 474 for (unsigned i = 0; i < (reg_size / 16); i++) { in MoveImmediateHelper() 512 int reg_size = dst.GetSizeInBits(); in OneInstrMoveImmediateHelper() local 514 if (IsImmMovz(imm, reg_size) && !dst.IsSP()) { in OneInstrMoveImmediateHelper() 521 } else if (IsImmMovn(imm, reg_size) && !dst.IsSP()) { in OneInstrMoveImmediateHelper() 528 } else if (IsImmLogical(imm, reg_size, &n, &imm_s, &imm_r)) { in OneInstrMoveImmediateHelper() 825 unsigned reg_size = rd.GetSizeInBits(); in LogicalMacro() local [all …]
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D | assembler-aarch64.h | 829 unsigned reg_size = rd.GetSizeInBits(); in lsl() local 830 VIXL_ASSERT(shift < reg_size); in lsl() 831 ubfm(rd, rn, (reg_size - shift) % reg_size, reg_size - shift - 1); in lsl() 3779 static Instr ImmS(unsigned imms, unsigned reg_size) { in ImmS() argument 3780 VIXL_ASSERT(((reg_size == kXRegSize) && IsUint6(imms)) || in ImmS() 3781 ((reg_size == kWRegSize) && IsUint5(imms))); in ImmS() 3782 USE(reg_size); in ImmS() 3786 static Instr ImmR(unsigned immr, unsigned reg_size) { in ImmR() argument 3787 VIXL_ASSERT(((reg_size == kXRegSize) && IsUint6(immr)) || in ImmR() 3788 ((reg_size == kWRegSize) && IsUint5(immr))); in ImmR() [all …]
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/external/u-boot/arch/arm/cpu/armv7/ |
D | mpu_v7r.c | 74 if (rgn->reg_size) in mpu_config() 75 val = (rgn->reg_size << REGION_SIZE_SHIFT) | ENABLE_REGION; in mpu_config()
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/external/jemalloc_new/include/jemalloc/internal/ |
D | size_classes.sh | 61 reg_size=$((${grp} + ${delta}*${ndelta})) 75 try_nregs=$((${try_slab_size} / ${reg_size})) 82 try_nregs=$((${try_slab_size} / ${reg_size})) 83 if [ ${perfect_slab_size} -eq $((${perfect_nregs} * ${reg_size})) ] ; then
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/external/mesa3d/src/mesa/drivers/dri/i965/ |
D | brw_performance_query.c | 457 uint32_t reg, uint32_t reg_size, in brw_perf_store_register() argument 460 if (reg_size == 8) { in brw_perf_store_register() 463 assert(reg_size == 4); in brw_perf_store_register() 469 uint32_t reg, uint32_t reg_size,
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/external/jemalloc/test/unit/ |
D | junk.c | 31 for (i = 0; i < bin_info->reg_size; i++) { in arena_dalloc_junk_small_intercept() 34 i, bin_info->reg_size); in arena_dalloc_junk_small_intercept()
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/external/u-boot/arch/arm/cpu/armv7m/ |
D | mpu.c | 42 | reg_config->reg_size << REGION_SIZE_SHIFT | ENABLE_REGION in mpu_config()
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/external/v8/src/diagnostics/arm64/ |
D | disasm-arm64.cc | 241 unsigned reg_size = in VisitLogicalImmediate() local 243 if (rn_is_zr && !IsMovzMovnImm(reg_size, instr->ImmLogical())) { in VisitLogicalImmediate() 268 bool DisassemblingDecoder::IsMovzMovnImm(unsigned reg_size, uint64_t value) { in IsMovzMovnImm() argument 269 DCHECK((reg_size == kXRegSizeInBits) || in IsMovzMovnImm() 270 ((reg_size == kWRegSizeInBits) && (value <= 0xFFFFFFFF))); in IsMovzMovnImm() 281 if ((reg_size == kXRegSizeInBits) && in IsMovzMovnImm() 288 if ((reg_size == kWRegSizeInBits) && (((value & 0xFFFF0000) == 0xFFFF0000) || in IsMovzMovnImm() 3781 unsigned reg_size; in SubstituteRegisterField() local 3792 reg_size = kWRegSizeInBits; in SubstituteRegisterField() 3796 reg_size = kXRegSizeInBits; in SubstituteRegisterField() [all …]
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/external/vixl/src/ |
D | utils-vixl.cc | 191 unsigned CountClearHalfWords(uint64_t imm, unsigned reg_size) { in CountClearHalfWords() argument 192 VIXL_ASSERT((reg_size % 8) == 0); in CountClearHalfWords() 194 for (unsigned i = 0; i < (reg_size / 16); i++) { in CountClearHalfWords()
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/external/vixl/test/aarch64/ |
D | test-utils-aarch64.h | 277 int reg_size, 285 int reg_size,
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D | test-utils-aarch64.cc | 355 int reg_size, in PopulateRegisterArray() argument 364 r[i] = Register(n, reg_size); in PopulateRegisterArray() 386 int reg_size, in PopulateVRegisterArray() argument 395 v[i] = VRegister(n, reg_size); in PopulateVRegisterArray()
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