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Searched refs:reg_size (Results 1 – 25 of 68) sorted by relevance

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/external/v8/src/codegen/arm64/
Dassembler-arm64-inl.h915 Instr Assembler::ImmS(unsigned imms, unsigned reg_size) {
916 DCHECK(((reg_size == kXRegSizeInBits) && is_uint6(imms)) ||
917 ((reg_size == kWRegSizeInBits) && is_uint5(imms)));
918 USE(reg_size);
922 Instr Assembler::ImmR(unsigned immr, unsigned reg_size) {
923 DCHECK(((reg_size == kXRegSizeInBits) && is_uint6(immr)) ||
924 ((reg_size == kWRegSizeInBits) && is_uint5(immr)));
925 USE(reg_size);
930 Instr Assembler::ImmSetBits(unsigned imms, unsigned reg_size) {
931 DCHECK((reg_size == kWRegSizeInBits) || (reg_size == kXRegSizeInBits));
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Dinstructions-arm64.cc79 static uint64_t RepeatBitsAcrossReg(unsigned reg_size, uint64_t value, in RepeatBitsAcrossReg() argument
83 DCHECK((reg_size == kWRegSizeInBits) || (reg_size == kXRegSizeInBits)); in RepeatBitsAcrossReg()
85 for (unsigned i = width; i < reg_size; i *= 2) { in RepeatBitsAcrossReg()
95 unsigned reg_size = SixtyFourBits() ? kXRegSizeInBits : kWRegSizeInBits; in ImmLogical() local
135 reg_size, RotateRight(bits, imm_r & mask, width), width); in ImmLogical()
Dmacro-assembler-arm64.cc104 unsigned reg_size = rd.SizeInBits(); in LogicalMacro() local
159 if (IsImmLogical(immediate, reg_size, &n, &imm_s, &imm_r)) { in LogicalMacro()
225 unsigned reg_size = rd.SizeInBits(); in Mov() local
236 if (CountClearHalfWords(~imm, reg_size) > in Mov()
237 CountClearHalfWords(imm, reg_size)) { in Mov()
249 DCHECK_EQ(reg_size % 16, 0); in Mov()
540 unsigned TurboAssembler::CountClearHalfWords(uint64_t imm, unsigned reg_size) { in CountClearHalfWords() argument
541 DCHECK_EQ(reg_size % 8, 0); in CountClearHalfWords()
543 for (unsigned i = 0; i < (reg_size / 16); i++) { in CountClearHalfWords()
554 bool TurboAssembler::IsImmMovz(uint64_t imm, unsigned reg_size) { in IsImmMovz() argument
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/external/mesa3d/src/gallium/drivers/iris/
Diris_perf.c60 uint32_t reg, uint32_t reg_size, in iris_perf_store_register_mem() argument
65 if (reg_size == 8) { in iris_perf_store_register_mem()
68 assert(reg_size == 4); in iris_perf_store_register_mem()
79 uint32_t reg, uint32_t reg_size,
/external/jemalloc_new/src/
Dbin.c8 #define BIN_INFO_bin_yes(reg_size, slab_size, nregs) \ argument
9 {reg_size, slab_size, nregs, BITMAP_INFO_INITIALIZER(nregs)},
10 #define BIN_INFO_bin_no(reg_size, slab_size, nregs) argument
Dandroid_je_mallinfo.c41 total_bytes += bin_infos[j].reg_size * bin->stats.curregs; in accumulate_small_allocs()
107 mi.ordblks = bin_infos[bidx].reg_size * bin->stats.curregs; in je_mallinfo_bin_info()
/external/mesa3d/src/intel/compiler/
Dbrw_fs_reg_allocate.cpp878 const unsigned reg_size = dst.component_size(bld.dispatch_width()) / in emit_unspill() local
880 assert(count % reg_size == 0); in emit_unspill()
882 for (unsigned i = 0; i < count / reg_size; i++) { in emit_unspill()
897 unspill_inst->size_written = reg_size * REG_SIZE; in emit_unspill()
903 BRW_DATAPORT_OWORD_BLOCK_DWORDS(reg_size * 8), in emit_unspill()
924 dst.offset += reg_size * REG_SIZE; in emit_unspill()
925 spill_offset += reg_size * REG_SIZE; in emit_unspill()
934 const unsigned reg_size = src.component_size(bld.dispatch_width()) / in emit_spill() local
936 assert(count % reg_size == 0); in emit_spill()
938 for (unsigned i = 0; i < count / reg_size; i++) { in emit_spill()
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Dbrw_ir_vec4.h433 const unsigned reg_size = in regs_read() local
435 return DIV_ROUND_UP(reg_offset(inst->src[i]) % reg_size + inst->size_read(i), in regs_read()
436 reg_size); in regs_read()
/external/jemalloc_new/test/unit/
Dslab.c17 (bin_info->reg_size * regind)); in TEST_BEGIN()
21 bin_info->reg_size); in TEST_BEGIN()
Djunk.c22 for (i = 0; i < bin_info->reg_size; i++) { in arena_dalloc_junk_small_intercept()
25 i, bin_info->reg_size); in arena_dalloc_junk_small_intercept()
/external/jemalloc/src/
Dandroid_je_mallinfo.c37 mi.uordblks += arena_bin_info[j].reg_size * bin->stats.curregs; in je_mallinfo()
73 mi.fsmblks += arena_bin_info[j].reg_size * bin->stats.curregs; in __mallinfo_arena_info()
92 mi.ordblks = arena_bin_info[bidx].reg_size * bin->stats.curregs; in __mallinfo_bin_info()
Dstats.c69 size_t reg_size, run_size, curregs; in stats_arena_bins_print() local
85 CTL_M2_GET("arenas.bin.0.size", j, &reg_size, size_t); in stats_arena_bins_print()
159 reg_size, j, curregs * reg_size, nmalloc, in stats_arena_bins_print()
169 reg_size, j, curregs * reg_size, nmalloc, in stats_arena_bins_print()
/external/vixl/src/aarch64/
Dinstructions-aarch64.cc33 static uint64_t RepeatBitsAcrossReg(unsigned reg_size, in RepeatBitsAcrossReg() argument
38 VIXL_ASSERT((reg_size == kWRegSize) || (reg_size == kXRegSize)); in RepeatBitsAcrossReg()
40 for (unsigned i = width; i < reg_size; i *= 2) { in RepeatBitsAcrossReg()
110 unsigned reg_size = GetSixtyFourBits() ? kXRegSize : kWRegSize; in GetImmLogical() local
149 return RepeatBitsAcrossReg(reg_size, in GetImmLogical()
Dsimulator-aarch64.cc342 uint64_t Simulator::AddWithCarry(unsigned reg_size, in AddWithCarry() argument
348 VIXL_ASSERT((reg_size == kXRegSize) || (reg_size == kWRegSize)); in AddWithCarry()
350 uint64_t max_uint = (reg_size == kWRegSize) ? kWMaxUInt : kXMaxUInt; in AddWithCarry()
351 uint64_t reg_mask = (reg_size == kWRegSize) ? kWRegMask : kXRegMask; in AddWithCarry()
352 uint64_t sign_mask = (reg_size == kWRegSize) ? kWSignMask : kXSignMask; in AddWithCarry()
359 ReadNzcv().SetN(CalcNFlag(result, reg_size)); in AddWithCarry()
381 int64_t Simulator::ShiftOperand(unsigned reg_size, in ShiftOperand() argument
385 VIXL_ASSERT((reg_size == kWRegSize) || (reg_size == kXRegSize)); in ShiftOperand()
392 if (reg_size == kXRegSize) { in ShiftOperand()
408 uvalue |= ~UINT64_C(0) << (reg_size - amount); in ShiftOperand()
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Dmacro-assembler-aarch64.cc444 unsigned reg_size = rd.GetSizeInBits(); in MoveImmediateHelper() local
455 if (CountClearHalfWords(~imm, reg_size) > in MoveImmediateHelper()
456 CountClearHalfWords(imm, reg_size)) { in MoveImmediateHelper()
472 VIXL_ASSERT((reg_size % 16) == 0); in MoveImmediateHelper()
474 for (unsigned i = 0; i < (reg_size / 16); i++) { in MoveImmediateHelper()
512 int reg_size = dst.GetSizeInBits(); in OneInstrMoveImmediateHelper() local
514 if (IsImmMovz(imm, reg_size) && !dst.IsSP()) { in OneInstrMoveImmediateHelper()
521 } else if (IsImmMovn(imm, reg_size) && !dst.IsSP()) { in OneInstrMoveImmediateHelper()
528 } else if (IsImmLogical(imm, reg_size, &n, &imm_s, &imm_r)) { in OneInstrMoveImmediateHelper()
825 unsigned reg_size = rd.GetSizeInBits(); in LogicalMacro() local
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Dassembler-aarch64.h829 unsigned reg_size = rd.GetSizeInBits(); in lsl() local
830 VIXL_ASSERT(shift < reg_size); in lsl()
831 ubfm(rd, rn, (reg_size - shift) % reg_size, reg_size - shift - 1); in lsl()
3779 static Instr ImmS(unsigned imms, unsigned reg_size) { in ImmS() argument
3780 VIXL_ASSERT(((reg_size == kXRegSize) && IsUint6(imms)) || in ImmS()
3781 ((reg_size == kWRegSize) && IsUint5(imms))); in ImmS()
3782 USE(reg_size); in ImmS()
3786 static Instr ImmR(unsigned immr, unsigned reg_size) { in ImmR() argument
3787 VIXL_ASSERT(((reg_size == kXRegSize) && IsUint6(immr)) || in ImmR()
3788 ((reg_size == kWRegSize) && IsUint5(immr))); in ImmR()
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/external/u-boot/arch/arm/cpu/armv7/
Dmpu_v7r.c74 if (rgn->reg_size) in mpu_config()
75 val = (rgn->reg_size << REGION_SIZE_SHIFT) | ENABLE_REGION; in mpu_config()
/external/jemalloc_new/include/jemalloc/internal/
Dsize_classes.sh61 reg_size=$((${grp} + ${delta}*${ndelta}))
75 try_nregs=$((${try_slab_size} / ${reg_size}))
82 try_nregs=$((${try_slab_size} / ${reg_size}))
83 if [ ${perfect_slab_size} -eq $((${perfect_nregs} * ${reg_size})) ] ; then
/external/mesa3d/src/mesa/drivers/dri/i965/
Dbrw_performance_query.c457 uint32_t reg, uint32_t reg_size, in brw_perf_store_register() argument
460 if (reg_size == 8) { in brw_perf_store_register()
463 assert(reg_size == 4); in brw_perf_store_register()
469 uint32_t reg, uint32_t reg_size,
/external/jemalloc/test/unit/
Djunk.c31 for (i = 0; i < bin_info->reg_size; i++) { in arena_dalloc_junk_small_intercept()
34 i, bin_info->reg_size); in arena_dalloc_junk_small_intercept()
/external/u-boot/arch/arm/cpu/armv7m/
Dmpu.c42 | reg_config->reg_size << REGION_SIZE_SHIFT | ENABLE_REGION in mpu_config()
/external/v8/src/diagnostics/arm64/
Ddisasm-arm64.cc241 unsigned reg_size = in VisitLogicalImmediate() local
243 if (rn_is_zr && !IsMovzMovnImm(reg_size, instr->ImmLogical())) { in VisitLogicalImmediate()
268 bool DisassemblingDecoder::IsMovzMovnImm(unsigned reg_size, uint64_t value) { in IsMovzMovnImm() argument
269 DCHECK((reg_size == kXRegSizeInBits) || in IsMovzMovnImm()
270 ((reg_size == kWRegSizeInBits) && (value <= 0xFFFFFFFF))); in IsMovzMovnImm()
281 if ((reg_size == kXRegSizeInBits) && in IsMovzMovnImm()
288 if ((reg_size == kWRegSizeInBits) && (((value & 0xFFFF0000) == 0xFFFF0000) || in IsMovzMovnImm()
3781 unsigned reg_size; in SubstituteRegisterField() local
3792 reg_size = kWRegSizeInBits; in SubstituteRegisterField()
3796 reg_size = kXRegSizeInBits; in SubstituteRegisterField()
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/external/vixl/src/
Dutils-vixl.cc191 unsigned CountClearHalfWords(uint64_t imm, unsigned reg_size) { in CountClearHalfWords() argument
192 VIXL_ASSERT((reg_size % 8) == 0); in CountClearHalfWords()
194 for (unsigned i = 0; i < (reg_size / 16); i++) { in CountClearHalfWords()
/external/vixl/test/aarch64/
Dtest-utils-aarch64.h277 int reg_size,
285 int reg_size,
Dtest-utils-aarch64.cc355 int reg_size, in PopulateRegisterArray() argument
364 r[i] = Register(n, reg_size); in PopulateRegisterArray()
386 int reg_size, in PopulateVRegisterArray() argument
395 v[i] = VRegister(n, reg_size); in PopulateVRegisterArray()

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