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Searched refs:res12 (Results 1 – 25 of 59) sorted by relevance

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/external/swiftshader/third_party/llvm-7.0/llvm/test/CodeGen/AArch64/
Dshadow-call-stack.ll40 %res12 = add i32 %res1, %res2
42 %res1234 = add i32 %res12, %res34
/external/swiftshader/third_party/llvm-7.0/llvm/test/Analysis/CostModel/SystemZ/
Dint-arith.ll19 %res12 = add <8 x i8> undef, undef
40 ; CHECK: Cost Model: Found an estimated cost of 1 for instruction: %res12 = add <8 x i8> undef, u…
65 %res12 = sub <8 x i8> undef, undef
86 ; CHECK: Cost Model: Found an estimated cost of 1 for instruction: %res12 = sub <8 x i8> undef, u…
111 %res12 = mul <8 x i8> undef, undef
132 ; CHECK: Cost Model: Found an estimated cost of 1 for instruction: %res12 = mul <8 x i8> undef, u…
157 %res12 = sdiv <8 x i8> undef, undef
178 ; CHECK: Cost Model: Found an estimated cost of 40 for instruction: %res12 = sdiv <8 x i8> undef,…
203 %res12 = srem <8 x i8> undef, undef
224 ; CHECK: Cost Model: Found an estimated cost of 40 for instruction: %res12 = srem <8 x i8> undef,…
[all …]
Dlogical.ll16 %res12 = and <8 x i8> undef, undef
37 ; CHECK: Cost Model: Found an estimated cost of 1 for instruction: %res12 = and <8 x i8> undef, u…
62 %res12 = ashr <8 x i8> undef, undef
83 ; CHECK: Cost Model: Found an estimated cost of 1 for instruction: %res12 = ashr <8 x i8> undef, …
108 %res12 = lshr <8 x i8> undef, undef
129 ; CHECK: Cost Model: Found an estimated cost of 1 for instruction: %res12 = lshr <8 x i8> undef, …
154 %res12 = or <8 x i8> undef, undef
175 ; CHECK: Cost Model: Found an estimated cost of 1 for instruction: %res12 = or <8 x i8> undef, un…
200 %res12 = shl <8 x i8> undef, undef
221 ; CHECK: Cost Model: Found an estimated cost of 1 for instruction: %res12 = shl <8 x i8> undef, u…
[all …]
/external/u-boot/arch/arm/mach-exynos/include/mach/
Ddmc.h84 unsigned char res12[0xC]; member
151 unsigned char res12[0x4]; member
245 unsigned char res12[0x4]; member
Dclock.h33 unsigned char res12[0x1fc]; member
263 unsigned char res12[0x1fc]; member
553 unsigned char res12[0xdc]; member
890 unsigned char res12[0xd8]; member
/external/libvpx/libvpx/vpx_dsp/mips/
Didct16x16_msa.c332 v8i16 res8, res9, res10, res11, res12, res13, res14, res15; in vpx_iadst16_1d_columns_addblk_msa() local
432 ILVR_B2_SH(zero, dst12, zero, dst13, res12, res13); in vpx_iadst16_1d_columns_addblk_msa()
433 ADD2(res12, out12, res13, out13, res12, res13); in vpx_iadst16_1d_columns_addblk_msa()
434 CLIP_SH2_0_255(res12, res13); in vpx_iadst16_1d_columns_addblk_msa()
435 PCKEV_B2_SH(res12, res12, res13, res13, res12, res13); in vpx_iadst16_1d_columns_addblk_msa()
436 ST8x1_UB(res12, dst + 2 * dst_stride); in vpx_iadst16_1d_columns_addblk_msa()
/external/llvm/test/Bitcode/
DmiscInstructions.3.2.ll108 ; CHECK-NEXT: %res12 = icmp eq <2 x i32> %vec1, %vec2
109 %res12 = icmp eq <2 x i32> %vec1, %vec2
150 ; CHECK-NEXT: %res12 = fcmp ueq float %x1, %x2
151 %res12 = fcmp ueq float %x1, %x2
DmemInstructions.3.2.ll63 ; CHECK-NEXT: %res12 = load volatile i8, i8* %ptr1, align 1, !invariant.load !1
64 %res12 = load volatile i8, i8* %ptr1, align 1, !invariant.load !1
119 ; CHECK-NEXT: %res12 = load atomic i8, i8* %ptr1 singlethread seq_cst, align 1
120 %res12 = load atomic i8, i8* %ptr1 singlethread seq_cst, align 1
274 ; CHECK-NEXT: %res12 = extractvalue { i32, i1 } [[TMP]], 0
275 %res12 = cmpxchg volatile i32* %ptr, i32 %cmp, i32 %new singlethread release monotonic
/external/swiftshader/third_party/llvm-7.0/llvm/test/Bitcode/
DmiscInstructions.3.2.ll108 ; CHECK-NEXT: %res12 = icmp eq <2 x i32> %vec1, %vec2
109 %res12 = icmp eq <2 x i32> %vec1, %vec2
150 ; CHECK-NEXT: %res12 = fcmp ueq float %x1, %x2
151 %res12 = fcmp ueq float %x1, %x2
DmemInstructions.3.2.ll63 ; CHECK-NEXT: %res12 = load volatile i8, i8* %ptr1, align 1, !invariant.load !1
64 %res12 = load volatile i8, i8* %ptr1, align 1, !invariant.load !1
119 ; CHECK-NEXT: %res12 = load atomic i8, i8* %ptr1 syncscope("singlethread") seq_cst, align 1
120 %res12 = load atomic i8, i8* %ptr1 syncscope("singlethread") seq_cst, align 1
274 ; CHECK-NEXT: %res12 = extractvalue { i32, i1 } [[TMP]], 0
275 …%res12 = cmpxchg volatile i32* %ptr, i32 %cmp, i32 %new syncscope("singlethread") release monotonic
/external/u-boot/arch/powerpc/include/asm/
Dimmap_86xx.h44 char res12[20]; member
166 char res12[4]; member
230 char res12[12]; member
322 char res12[4]; member
546 char res12[12]; member
885 char res12[32]; member
1112 char res12[12]; member
Dimmap_83xx.h535 u8 res12[0x100]; member
572 u8 res12[0x160]; member
759 u8 res12[0x1CF00]; member
962 u8 res12[0xC1000]; member
/external/u-boot/arch/arm/include/asm/arch-sunxi/
Dcpucfg.h60 u8 res12[0x34]; /* 0x24c */ member
Dprcm.h237 u8 res12[0xc]; /* 0x184 */ member
/external/u-boot/include/linux/mtd/
Dsamsung_onenand.h40 unsigned char res12[0xc]; member
/external/swiftshader/third_party/subzero/crosstest/
Dtest_vector_ops_ll.ll173 %res12 = zext <16 x i1> %res12_i1 to <16 x i8>
174 ret <16 x i8> %res12
327 %res12 = insertelement <16 x i8> %vec, i8 %elt, i32 12
328 ret <16 x i8> %res12
517 %res12 = zext i1 %res12_i1 to i64
518 ret i64 %res12
693 %res12 = zext i8 %res12_i8 to i64
694 ret i64 %res12
/external/clang/test/SemaCXX/
Daltivec.cpp31 int res12[vec_step(vf) == 4 ? 1 : -1]; in test_vec_step() local
/external/clang/test/SemaOpenCL/
Dvec_step.cl27 int res12[vec_step(void) == 1 ? 1 : -1];
/external/u-boot/arch/m68k/include/asm/
Dimmap_5307.h85 u16 res12; member
/external/u-boot/arch/m68k/include/asm/coldfire/
Dflexbus.h50 u16 res12; member
/external/u-boot/board/freescale/common/
Dqixis.h75 u8 res12[3]; member
/external/u-boot/drivers/crypto/
Dace_sha.h71 unsigned char res12[0x30]; member
/external/u-boot/include/usb/
Dehci-ci.h237 u8 res12[0x1F8]; member
/external/u-boot/include/linux/
Dimmap_qe.h103 u8 res12[0x2]; member
573 u8 res12[0x600]; member
/external/u-boot/drivers/net/
Dfec_mxc.h66 uint32_t res12[29]; /* MBAR_ETH + 0x18C-1FC */ member

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