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/external/swiftshader/third_party/llvm-7.0/llvm/test/Analysis/CostModel/SystemZ/
Dint-arith.ll22 %res15 = add <8 x i64> undef, undef
43 ; CHECK: Cost Model: Found an estimated cost of 4 for instruction: %res15 = add <8 x i64> undef, …
68 %res15 = sub <8 x i64> undef, undef
89 ; CHECK: Cost Model: Found an estimated cost of 4 for instruction: %res15 = sub <8 x i64> undef, …
114 %res15 = mul <8 x i64> undef, undef
135 ; CHECK: Cost Model: Found an estimated cost of 12 for instruction: %res15 = mul <8 x i64> undef,…
160 %res15 = sdiv <8 x i64> undef, undef
181 ; CHECK: Cost Model: Found an estimated cost of 12 for instruction: %res15 = sdiv <8 x i64> undef…
206 %res15 = srem <8 x i64> undef, undef
227 ; CHECK: Cost Model: Found an estimated cost of 12 for instruction: %res15 = srem <8 x i64> undef…
[all …]
Dlogical.ll19 %res15 = and <8 x i64> undef, undef
40 ; CHECK: Cost Model: Found an estimated cost of 4 for instruction: %res15 = and <8 x i64> undef, …
65 %res15 = ashr <8 x i64> undef, undef
86 ; CHECK: Cost Model: Found an estimated cost of 4 for instruction: %res15 = ashr <8 x i64> undef,…
111 %res15 = lshr <8 x i64> undef, undef
132 ; CHECK: Cost Model: Found an estimated cost of 4 for instruction: %res15 = lshr <8 x i64> undef,…
157 %res15 = or <8 x i64> undef, undef
178 ; CHECK: Cost Model: Found an estimated cost of 4 for instruction: %res15 = or <8 x i64> undef, u…
203 %res15 = shl <8 x i64> undef, undef
224 ; CHECK: Cost Model: Found an estimated cost of 4 for instruction: %res15 = shl <8 x i64> undef, …
[all …]
/external/u-boot/arch/arm/mach-exynos/include/mach/
Ddmc.h90 unsigned char res15[0xEBC]; member
157 unsigned char res15[0x4]; member
251 unsigned char res15[0x4]; member
Dclock.h40 unsigned char res15[0xc]; member
270 unsigned char res15[0x3608]; member
573 unsigned char res15[0xfc]; member
918 unsigned char res15[0xe0]; member
/external/libvpx/libvpx/vpx_dsp/mips/
Didct16x16_msa.c332 v8i16 res8, res9, res10, res11, res12, res13, res14, res15; in vpx_iadst16_1d_columns_addblk_msa() local
480 ILVR_B2_SH(zero, dst14, zero, dst15, res14, res15); in vpx_iadst16_1d_columns_addblk_msa()
481 ADD2(res14, out14, res15, out15, res14, res15); in vpx_iadst16_1d_columns_addblk_msa()
482 CLIP_SH2_0_255(res14, res15); in vpx_iadst16_1d_columns_addblk_msa()
483 PCKEV_B2_SH(res14, res14, res15, res15, res14, res15); in vpx_iadst16_1d_columns_addblk_msa()
485 ST8x1_UB(res15, dst + 10 * dst_stride); in vpx_iadst16_1d_columns_addblk_msa()
/external/u-boot/drivers/net/
Dfec_mxc.h133 uint16_t res15[3]; /* MBAR_ETH + 0x302-306 */ member
138 uint32_t res15[64]; /* MBAR_ETH + 0x300-3FF */ member
/external/u-boot/include/linux/mtd/
Dsamsung_onenand.h46 unsigned char res15[0xc]; member
/external/u-boot/arch/powerpc/include/asm/
Dimmap_86xx.h50 char res15[4]; member
171 char res15[4]; member
236 char res15[236]; member
328 char res15[4]; member
552 char res15[12]; member
898 char res15[12]; member
Dimmap_85xx.h78 u8 res15[4]; member
317 u8 res15[420]; member
383 u8 res15[56]; member
652 u8 res15[12]; member
1747 u8 res15[4]; member
2104 u8 res15[4]; member
2502 u8 res15[12]; member
2507 u8 res15[248]; member
/external/swiftshader/third_party/llvm-7.0/llvm/test/Bitcode/
DmemInstructions.3.2.ll72 ; CHECK-NEXT: %res15 = load i8, i8* %ptr1, align 1, {{[(!nontemporal !0, !invariant.load !1) | (!in…
73 %res15 = load i8, i8* %ptr1, align 1, !nontemporal !0, !invariant.load !1
128 ; CHECK-NEXT: %res15 = load atomic volatile i8, i8* %ptr1 syncscope("singlethread") acquire, align 1
129 %res15 = load atomic volatile i8, i8* %ptr1 syncscope("singlethread") acquire, align 1
287 ; CHECK-NEXT: %res15 = extractvalue { i32, i1 } [[TMP]], 0
288 %res15 = cmpxchg i32* %ptr, i32 %cmp, i32 %new syncscope("singlethread") acq_rel acquire
DmiscInstructions.3.2.ll159 ; CHECK-NEXT: %res15 = fcmp true float %x1, %x2
160 %res15 = fcmp true float %x1, %x2
/external/llvm/test/Bitcode/
DmemInstructions.3.2.ll72 ; CHECK-NEXT: %res15 = load i8, i8* %ptr1, align 1, {{[(!nontemporal !0, !invariant.load !1) | (!in…
73 %res15 = load i8, i8* %ptr1, align 1, !nontemporal !0, !invariant.load !1
128 ; CHECK-NEXT: %res15 = load atomic volatile i8, i8* %ptr1 singlethread acquire, align 1
129 %res15 = load atomic volatile i8, i8* %ptr1 singlethread acquire, align 1
287 ; CHECK-NEXT: %res15 = extractvalue { i32, i1 } [[TMP]], 0
288 %res15 = cmpxchg i32* %ptr, i32 %cmp, i32 %new singlethread acq_rel acquire
DmiscInstructions.3.2.ll159 ; CHECK-NEXT: %res15 = fcmp true float %x1, %x2
160 %res15 = fcmp true float %x1, %x2
/external/swiftshader/third_party/subzero/crosstest/
Dtest_vector_ops_ll.ll185 %res15 = zext <16 x i1> %res15_i1 to <16 x i8>
186 ret <16 x i8> %res15
336 %res15 = insertelement <16 x i8> %vec, i8 %elt, i32 15
337 ret <16 x i8> %res15
529 %res15 = zext i1 %res15_i1 to i64
530 ret i64 %res15
705 %res15 = zext i8 %res15_i8 to i64
706 ret i64 %res15
/external/clang/test/SemaOpenCL/
Dvec_step.cl31 …int res15 = vec_step(void(void)); // expected-error {{'vec_step' requires built-in scalar or vecto…
/external/u-boot/arch/m68k/include/asm/
Dimmap_5307.h93 u16 res15; member
/external/u-boot/arch/m68k/include/asm/coldfire/
Dflexbus.h60 u16 res15; member
/external/u-boot/board/freescale/common/
Dqixis.h88 u8 res15[16]; member
/external/u-boot/drivers/crypto/
Dace_sha.h77 unsigned char res15[0x18c]; member
/external/swiftshader/third_party/llvm-7.0/llvm/test/CodeGen/SystemZ/
Dint-uadd-10.ll262 %res15 = or i1 %res14, %obit15
283 %res = phi i1 [ 0, %entry ], [ %res15, %add ]
394 %res15 = or i1 %res14, %obit15
415 %res = phi i1 [ 0, %entry ], [ %res15, %add ]
Dint-sadd-09.ll272 %res15 = or i1 %res14, %obit15
293 %res = phi i1 [ 0, %entry ], [ %res15, %add ]
404 %res15 = or i1 %res14, %obit15
425 %res = phi i1 [ 0, %entry ], [ %res15, %add ]
Dint-ssub-08.ll272 %res15 = or i1 %res14, %obit15
293 %res = phi i1 [ 0, %entry ], [ %res15, %add ]
404 %res15 = or i1 %res14, %obit15
425 %res = phi i1 [ 0, %entry ], [ %res15, %add ]
Dint-ssub-09.ll272 %res15 = or i1 %res14, %obit15
293 %res = phi i1 [ 0, %entry ], [ %res15, %add ]
404 %res15 = or i1 %res14, %obit15
425 %res = phi i1 [ 0, %entry ], [ %res15, %add ]
Dint-sadd-08.ll272 %res15 = or i1 %res14, %obit15
293 %res = phi i1 [ 0, %entry ], [ %res15, %add ]
404 %res15 = or i1 %res14, %obit15
425 %res = phi i1 [ 0, %entry ], [ %res15, %add ]
Dint-usub-10.ll272 %res15 = or i1 %res14, %obit15
293 %res = phi i1 [ 0, %entry ], [ %res15, %add ]
404 %res15 = or i1 %res14, %obit15
425 %res = phi i1 [ 0, %entry ], [ %res15, %add ]

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