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Searched refs:res3 (Results 1 – 25 of 268) sorted by relevance

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/external/libvpx/libvpx/vp8/common/mips/msa/
Didct_msa.c91 v4i32 res0, res1, res2, res3; in idct4x4_addblk_msa() local
105 res2, res3); in idct4x4_addblk_msa()
106 ILVR_H4_SW(zero, res0, zero, res1, zero, res2, zero, res3, res0, res1, res2, in idct4x4_addblk_msa()
107 res3); in idct4x4_addblk_msa()
108 ADD4(res0, vt0, res1, vt1, res2, vt2, res3, vt3, res0, res1, res2, res3); in idct4x4_addblk_msa()
112 res3 = CLIP_SW_0_255(res3); in idct4x4_addblk_msa()
113 PCKEV_B2_SW(res0, res1, res2, res3, vt0, vt1); in idct4x4_addblk_msa()
121 v8i16 vec, res0, res1, res2, res3, dst0, dst1; in idct4x4_addconst_msa() local
129 res2, res3); in idct4x4_addconst_msa()
130 ADD4(res0, vec, res1, vec, res2, vec, res3, vec, res0, res1, res2, res3); in idct4x4_addconst_msa()
[all …]
/external/u-boot/arch/powerpc/include/asm/
Dimmap_8xx.h30 char res3[0x4c]; member
58 char res3[4]; member
91 char res3[0x80]; member
107 char res3[0x10]; member
162 char res3[0x38]; member
186 char res3[3]; member
201 char res3[3]; member
241 char res3[2]; member
287 char res3; member
297 char res3[3]; member
[all …]
Dimmap_83xx.h42 u8 res3[0x10]; member
307 u8 res3[0x14]; member
368 u32 res3[0x5]; /* 0x6C-0x79 reserved */ member
432 u8 res3[4]; member
494 u8 res3[0x98]; member
554 u8 res3[4]; member
653 u8 res3[0x900]; member
702 u8 res3[0x1000]; member
737 u8 res3[0x1000]; member
781 u8 res3[0x900]; member
[all …]
/external/libaom/libaom/av1/common/arm/
Dwiener_convolve_neon.c79 int16x8_t res0, res1, res2, res3; in av1_wiener_convolve_add_src_neon() local
121 res3 = vreinterpretq_s16_u16(vmovl_u8(t3)); in av1_wiener_convolve_add_src_neon()
122 res4 = wiener_convolve8_horiz_8x8(res0, res1, res2, res3, filter_x_tmp, in av1_wiener_convolve_add_src_neon()
128 res3 = vreinterpretq_s16_u16(vmovl_u8(t4)); in av1_wiener_convolve_add_src_neon()
129 res5 = wiener_convolve8_horiz_8x8(res0, res1, res2, res3, filter_x_tmp, in av1_wiener_convolve_add_src_neon()
135 res3 = vreinterpretq_s16_u16(vmovl_u8(t5)); in av1_wiener_convolve_add_src_neon()
136 res6 = wiener_convolve8_horiz_8x8(res0, res1, res2, res3, filter_x_tmp, in av1_wiener_convolve_add_src_neon()
142 res3 = vreinterpretq_s16_u16(vmovl_u8(t6)); in av1_wiener_convolve_add_src_neon()
143 res7 = wiener_convolve8_horiz_8x8(res0, res1, res2, res3, filter_x_tmp, in av1_wiener_convolve_add_src_neon()
149 res3 = vreinterpretq_s16_u16(vmovl_u8(t7)); in av1_wiener_convolve_add_src_neon()
[all …]
/external/swiftshader/third_party/llvm-7.0/llvm/test/Bitcode/
DbinaryIntInstructions.3.2.ll16 ; CHECK-NEXT: %res3 = add i16 %x3, %x3
17 %res3 = add i16 %x3, %x3
45 ; CHECK-NEXT: %res3 = add nuw nsw <4 x i8> %x3, %x3
46 %res3 = add nuw nsw <4 x i8> %x3, %x3
65 ; CHECK-NEXT: %res3 = add nuw nsw <4 x i16> %x3, %x3
66 %res3 = add nuw nsw <4 x i16> %x3, %x3
85 ; CHECK-NEXT: %res3 = add nuw nsw <4 x i32> %x3, %x3
86 %res3 = add nuw nsw <4 x i32> %x3, %x3
105 ; CHECK-NEXT: %res3 = add nuw nsw <4 x i64> %x3, %x3
106 %res3 = add nuw nsw <4 x i64> %x3, %x3
[all …]
DbinaryFloatInstructions.3.2.ll16 ; CHECK-NEXT: %res3 = fadd half %x3, %x3
17 %res3 = fadd half %x3, %x3
39 ; CHECK-NEXT: %res3 = fadd <4 x float> %x3, %x3
40 %res3 = fadd <4 x float> %x3, %x3
59 ; CHECK-NEXT: %res3 = fadd <4 x double> %x3, %x3
60 %res3 = fadd <4 x double> %x3, %x3
79 ; CHECK-NEXT: %res3 = fadd <4 x half> %x3, %x3
80 %res3 = fadd <4 x half> %x3, %x3
/external/llvm/test/Bitcode/
DbinaryIntInstructions.3.2.ll16 ; CHECK-NEXT: %res3 = add i16 %x3, %x3
17 %res3 = add i16 %x3, %x3
45 ; CHECK-NEXT: %res3 = add nuw nsw <4 x i8> %x3, %x3
46 %res3 = add nuw nsw <4 x i8> %x3, %x3
65 ; CHECK-NEXT: %res3 = add nuw nsw <4 x i16> %x3, %x3
66 %res3 = add nuw nsw <4 x i16> %x3, %x3
85 ; CHECK-NEXT: %res3 = add nuw nsw <4 x i32> %x3, %x3
86 %res3 = add nuw nsw <4 x i32> %x3, %x3
105 ; CHECK-NEXT: %res3 = add nuw nsw <4 x i64> %x3, %x3
106 %res3 = add nuw nsw <4 x i64> %x3, %x3
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DbinaryFloatInstructions.3.2.ll16 ; CHECK-NEXT: %res3 = fadd half %x3, %x3
17 %res3 = fadd half %x3, %x3
39 ; CHECK-NEXT: %res3 = fadd <4 x float> %x3, %x3
40 %res3 = fadd <4 x float> %x3, %x3
59 ; CHECK-NEXT: %res3 = fadd <4 x double> %x3, %x3
60 %res3 = fadd <4 x double> %x3, %x3
79 ; CHECK-NEXT: %res3 = fadd <4 x half> %x3, %x3
80 %res3 = fadd <4 x half> %x3, %x3
/external/Reactive-Extensions/RxCpp/Rx/v2/test/operators/
Dreplay.cpp269 auto res3 = w.make_subscriber<int>(); variable
270 w.schedule_absolute(600, [&ys, &res3](const rxsc::schedulable&){ys.subscribe(res3);}); in __anon0ead19a21602()
330 auto actual = res3.get_observer().messages();
399 auto res3 = w.make_subscriber<int>(); variable
400 w.schedule_absolute(600, [&ys, &res3](const rxsc::schedulable&){ys.subscribe(res3);}); in __anon0ead19a21c02()
447 auto actual = res3.get_observer().messages();
518 auto res3 = w.make_subscriber<int>(); variable
519 w.schedule_absolute(600, [&ys, &res3](const rxsc::schedulable&){ys.subscribe(res3);}); in __anon0ead19a22202()
566 auto actual = res3.get_observer().messages();
637 auto res3 = w.make_subscriber<int>(); variable
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/external/eigen/unsupported/test/
Dautodiff_scalar.cpp58 AD res3 = cosh(val); in check_hyperbolic_functions() local
59 VERIFY_IS_APPROX(res3.value(), cosh_px); in check_hyperbolic_functions()
60 VERIFY_IS_APPROX(res3.derivatives().x(), std::sinh(p.x())); in check_hyperbolic_functions()
71 res3 = cosh(val); in check_hyperbolic_functions()
72 VERIFY_IS_APPROX(res3.derivatives().x(), Scalar(0.339540557256150)); in check_hyperbolic_functions()
/external/u-boot/arch/arm/include/asm/arch-omap3/
Dcpu.h26 u8 res3[0x08]; member
105 u8 res3[0x84]; member
124 u8 res3[0x4]; member
139 u8 res3[0x18]; member
166 unsigned char res3[32]; member
249 u8 res3[0x4]; member
317 u8 res3[0x8bc]; member
404 u8 res3[0x1c]; member
451 u8 res3[0x4]; member
/external/libaom/libaom/av1/encoder/x86/
Dhighbd_block_error_intrin_avx2.c40 __m256i res3 = _mm256_mul_epi32(diff2h, diff2h); in av1_highbd_block_error_avx2() local
42 _mm256_add_epi64(res2, res3)); in av1_highbd_block_error_avx2()
48 res3 = _mm256_mul_epi32(mm256_coeffh2, mm256_coeffh2); in av1_highbd_block_error_avx2()
50 _mm256_add_epi64(res2, res3)); in av1_highbd_block_error_avx2()
/external/swiftshader/third_party/subzero/crosstest/
Dtest_vector_ops_ll.ll18 %res3 = insertelement <4 x float> %vec, float %elt, i32 3
19 ret <4 x float> %res3
47 %res3 = zext <4 x i1> %res3_i1 to <4 x i32>
48 ret <4 x i32> %res3
80 %res3 = zext <8 x i1> %res3_i1 to <8 x i16>
81 ret <8 x i16> %res3
137 %res3 = zext <16 x i1> %res3_i1 to <16 x i8>
138 ret <16 x i8> %res3
210 %res3 = insertelement <4 x i32> %vec, i32 %elt, i32 3
211 ret <4 x i32> %res3
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/external/swiftshader/third_party/subzero/tests_lit/assembler/x86/
Dopcode_register_encodings.ll24 %res3 = sub <8 x i16> %arg0, %arg3
31 %res_acc2 = select <8 x i1> %cond, <8 x i16> %res3, <8 x i16> %res4
64 %res3 = sub <4 x i32> %arg0, %arg3
71 %res_acc2 = select <4 x i1> %cond, <4 x i32> %res3, <4 x i32> %res4
128 %res3 = load <16 x i8>, <16 x i8>* %addr3_v16xI8, align 1
130 %res123 = add <16 x i8> %res12, %res3
180 %res3 = insertelement <4 x i32> %res2, i32 %elt1, i32 3
181 ret <4 x i32> %res3
199 %res3 = insertelement <16 x i8> %res2, i8 %elt1, i32 15
200 ret <16 x i8> %res3
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/external/u-boot/include/
Dfis.h52 u8 res3[4]; member
74 u8 res3[4]; member
87 u32 res3; member
111 u8 res3; member
/external/libaom/libaom/aom_dsp/x86/
Dmasked_sad4d_ssse3.c52 __m128i res3 = _mm_setzero_si128(); in masked_sadx4d_ssse3() local
83 res2 = _mm_add_epi32(_mm_unpacklo_epi32(res2, res3), in masked_sadx4d_ssse3()
84 _mm_unpackhi_epi32(res2, res3)); in masked_sadx4d_ssse3()
119 __m128i res3 = _mm_setzero_si128(); in aom_masked_sad8xhx4d_ssse3() local
150 res2 = _mm_add_epi32(_mm_unpacklo_epi32(res2, res3), in aom_masked_sad8xhx4d_ssse3()
151 _mm_unpackhi_epi32(res2, res3)); in aom_masked_sad8xhx4d_ssse3()
180 __m128i res3 = _mm_setzero_si128(); in aom_masked_sad4xhx4d_ssse3() local
213 res2 = _mm_unpacklo_epi32(res2, res3); in aom_masked_sad4xhx4d_ssse3()
/external/u-boot/arch/m68k/include/asm/coldfire/
Dpwm.h20 u8 res3[7]; member
40 u16 res3; /* 0x10 - 0x11 */
49 u8 res3[3]; /* 0x25 - 0x27 */
/external/llvm/test/CodeGen/X86/
Dmerge-consecutive-loads-512.ll132 %res3 = insertelement <8 x double> %res2, double 0.0, i32 3
133 %res6 = insertelement <8 x double> %res3, double 0.0, i32 6
218 %res3 = insertelement <8 x i64> %res2, i64 0, i32 3
219 %res4 = insertelement <8 x i64> %res3, i64 %val4, i32 4
276 %res3 = insertelement <16 x float> %res2, float 0.0, i32 3
277 %res4 = insertelement <16 x float> %res3, float 0.0, i32 4
301 %res3 = insertelement <16 x float> %res1, float %val3, i32 3
302 ret <16 x float> %res3
327 %res3 = insertelement <16 x float> %res0, float %val3, i32 3
328 %resC = insertelement <16 x float> %res3, float %valC, i32 12
[all …]
Davx512ifmavl-intrinsics.ll25 …%res3 = call <2 x i64> @llvm.x86.avx512.mask.vpmadd52h.uq.128(<2 x i64> %x0, <2 x i64> %x1, <2 x i…
27 %res5 = add <2 x i64> %res3, %res2
53 …%res3 = call <4 x i64> @llvm.x86.avx512.mask.vpmadd52h.uq.256(<4 x i64> %x0, <4 x i64> %x1, <4 x i…
55 %res5 = add <4 x i64> %res3, %res2
81 …%res3 = call <2 x i64> @llvm.x86.avx512.maskz.vpmadd52h.uq.128(<2 x i64> %x0, <2 x i64> %x1, <2 x …
83 %res5 = add <2 x i64> %res3, %res2
109 …%res3 = call <4 x i64> @llvm.x86.avx512.maskz.vpmadd52h.uq.256(<4 x i64> %x0, <4 x i64> %x1, <4 x …
111 %res5 = add <4 x i64> %res3, %res2
137 …%res3 = call <2 x i64> @llvm.x86.avx512.mask.vpmadd52l.uq.128(<2 x i64> %x0, <2 x i64> %x1, <2 x i…
139 %res5 = add <2 x i64> %res3, %res2
[all …]
Davx512vbmi-intrinsics.ll18 %res3 = add <64 x i8> %res, %res1
19 %res4 = add <64 x i8> %res3, %res2
35 %res3 = add <64 x i8> %res, %res1
36 %res4 = add <64 x i8> %res3, %res2
57 %res3 = add <64 x i8> %res, %res1
58 %res4 = add <64 x i8> %res3, %res2
79 %res3 = add <64 x i8> %res, %res1
80 %res4 = add <64 x i8> %res3, %res2
Davx512vbmivl-intrinsics.ll18 %res3 = add <16 x i8> %res, %res1
19 %res4 = add <16 x i8> %res3, %res2
38 %res3 = add <32 x i8> %res, %res1
39 %res4 = add <32 x i8> %res3, %res2
58 %res3 = add <16 x i8> %res, %res1
59 %res4 = add <16 x i8> %res3, %res2
78 %res3 = add <32 x i8> %res, %res1
79 %res4 = add <32 x i8> %res3, %res2
100 %res3 = add <16 x i8> %res, %res1
101 %res4 = add <16 x i8> %res3, %res2
[all …]
/external/swiftshader/third_party/llvm-7.0/llvm/test/CodeGen/X86/
Dmerge-consecutive-loads-512.ll124 %res3 = insertelement <8 x double> %res2, double 0.0, i32 3
125 %res6 = insertelement <8 x double> %res3, double 0.0, i32 6
214 %res3 = insertelement <8 x i64> %res2, i64 0, i32 3
215 %res4 = insertelement <8 x i64> %res3, i64 %val4, i32 4
280 %res3 = insertelement <16 x float> %res2, float 0.0, i32 3
281 %res4 = insertelement <16 x float> %res3, float 0.0, i32 4
305 %res3 = insertelement <16 x float> %res1, float %val3, i32 3
306 ret <16 x float> %res3
331 %res3 = insertelement <16 x float> %res0, float %val3, i32 3
332 %resC = insertelement <16 x float> %res3, float %valC, i32 12
[all …]
/external/icu/icu4c/source/test/intltest/
Dnmfmapts.cpp124 UnicodeString res1, res2, res3, res4, res5, res6; in testAPI() local
133 res3 = cur_fr->format(d, res3, pos1); in testAPI()
134 logln( (UnicodeString) "" + (int32_t) d + " formatted to " + res3); in testAPI()
332 UnicodeString res0, res1, res2, res3, res4, res5; in testRegistration() local
340 f3->format(n, res3); in testRegistration()
351 logln((UnicodeString)"f3 reg cur: " + res3); in testRegistration()
365 if (res3 != res0) { in testRegistration()
/external/swiftshader/third_party/llvm-7.0/llvm/test/Analysis/CostModel/SystemZ/
Dfp-arith.ll15 %res3 = fadd <2 x float> undef, undef
27 ; CHECK-Z13: Cost Model: Found an estimated cost of 8 for instruction: %res3 = fadd <2 x float> u…
28 ; CHECK-Z14: Cost Model: Found an estimated cost of 1 for instruction: %res3 = fadd <2 x float> u…
47 %res3 = fsub <2 x float> undef, undef
59 ; CHECK-Z13: Cost Model: Found an estimated cost of 8 for instruction: %res3 = fsub <2 x float> u…
60 ; CHECK-Z14: Cost Model: Found an estimated cost of 1 for instruction: %res3 = fsub <2 x float> u…
79 %res3 = fmul <2 x float> undef, undef
91 ; CHECK-Z13: Cost Model: Found an estimated cost of 8 for instruction: %res3 = fmul <2 x float> u…
92 ; CHECK-Z14: Cost Model: Found an estimated cost of 1 for instruction: %res3 = fmul <2 x float> u…
111 %res3 = fdiv <2 x float> undef, undef
[all …]
/external/u-boot/include/linux/
Dimmap_qe.h67 u8 res3[0x1C]; member
86 u8 res3[0x2]; member
179 u8 res3[0x2]; member
201 u8 res3[0x1]; member
256 u8 res3[2]; member
288 u8 res3[0x24]; member
325 u8 res3[0x180 - 0x15A]; member
393 u8 res3[0x2]; member
549 u8 res3[4]; member

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