1 /* SPDX-License-Identifier: GPL-2.0+ */ 2 /* 3 * Copyright 2013-2015 Freescale Semiconductor, Inc. 4 */ 5 6 #ifndef __ARCH_FSL_LSCH2_IMMAP_H__ 7 #define __ARCH_FSL_LSCH2_IMMAP_H__ 8 9 #include <fsl_immap.h> 10 11 #define CONFIG_SYS_IMMR 0x01000000 12 #define CONFIG_SYS_DCSRBAR 0x20000000 13 #define CONFIG_SYS_DCSR_DCFG_ADDR (CONFIG_SYS_DCSRBAR + 0x00140000) 14 #define CONFIG_SYS_DCSR_COP_CCP_ADDR (CONFIG_SYS_DCSRBAR + 0x02008040) 15 16 #define CONFIG_SYS_FSL_DDR_ADDR (CONFIG_SYS_IMMR + 0x00080000) 17 #define CONFIG_SYS_GIC400_ADDR (CONFIG_SYS_IMMR + 0x00400000) 18 #define CONFIG_SYS_IFC_ADDR (CONFIG_SYS_IMMR + 0x00530000) 19 #define SYS_FSL_QSPI_ADDR (CONFIG_SYS_IMMR + 0x00550000) 20 #define CONFIG_SYS_FSL_ESDHC_ADDR (CONFIG_SYS_IMMR + 0x00560000) 21 #define CONFIG_SYS_FSL_CSU_ADDR (CONFIG_SYS_IMMR + 0x00510000) 22 #define CONFIG_SYS_FSL_GUTS_ADDR (CONFIG_SYS_IMMR + 0x00ee0000) 23 #define CONFIG_SYS_FSL_RST_ADDR (CONFIG_SYS_IMMR + 0x00ee00b0) 24 #define CONFIG_SYS_FSL_SCFG_ADDR (CONFIG_SYS_IMMR + 0x00570000) 25 #define CONFIG_SYS_FSL_BMAN_ADDR (CONFIG_SYS_IMMR + 0x00890000) 26 #define CONFIG_SYS_FSL_QMAN_ADDR (CONFIG_SYS_IMMR + 0x00880000) 27 #define CONFIG_SYS_FSL_FMAN_ADDR (CONFIG_SYS_IMMR + 0x00a00000) 28 #define CONFIG_SYS_FSL_SERDES_ADDR (CONFIG_SYS_IMMR + 0x00ea0000) 29 #define CONFIG_SYS_FSL_DCFG_ADDR (CONFIG_SYS_IMMR + 0x00ee0000) 30 #define CONFIG_SYS_FSL_CLK_ADDR (CONFIG_SYS_IMMR + 0x00ee1000) 31 #define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_IMMR + 0x011c0500) 32 #define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_IMMR + 0x011c0600) 33 #define CONFIG_SYS_NS16550_COM3 (CONFIG_SYS_IMMR + 0x011d0500) 34 #define CONFIG_SYS_NS16550_COM4 (CONFIG_SYS_IMMR + 0x011d0600) 35 #define CONFIG_SYS_XHCI_USB1_ADDR (CONFIG_SYS_IMMR + 0x01f00000) 36 #define CONFIG_SYS_XHCI_USB2_ADDR (CONFIG_SYS_IMMR + 0x02000000) 37 #define CONFIG_SYS_XHCI_USB3_ADDR (CONFIG_SYS_IMMR + 0x02100000) 38 #define CONFIG_SYS_EHCI_USB1_ADDR (CONFIG_SYS_IMMR + 0x07600000) 39 #define CONFIG_SYS_PCIE1_ADDR (CONFIG_SYS_IMMR + 0x2400000) 40 #define CONFIG_SYS_PCIE2_ADDR (CONFIG_SYS_IMMR + 0x2500000) 41 #define CONFIG_SYS_PCIE3_ADDR (CONFIG_SYS_IMMR + 0x2600000) 42 #define CONFIG_SYS_SEC_MON_ADDR (CONFIG_SYS_IMMR + 0xe90000) 43 #define CONFIG_SYS_SFP_ADDR (CONFIG_SYS_IMMR + 0xe80200) 44 45 #define CONFIG_SYS_BMAN_NUM_PORTALS 10 46 #define CONFIG_SYS_BMAN_MEM_BASE 0x508000000 47 #define CONFIG_SYS_BMAN_MEM_PHYS (0xf00000000ull + \ 48 CONFIG_SYS_BMAN_MEM_BASE) 49 #define CONFIG_SYS_BMAN_MEM_SIZE 0x08000000 50 #define CONFIG_SYS_BMAN_SP_CENA_SIZE 0x10000 51 #define CONFIG_SYS_BMAN_SP_CINH_SIZE 0x10000 52 #define CONFIG_SYS_BMAN_CENA_BASE CONFIG_SYS_BMAN_MEM_BASE 53 #define CONFIG_SYS_BMAN_CENA_SIZE (CONFIG_SYS_BMAN_MEM_SIZE >> 1) 54 #define CONFIG_SYS_BMAN_CINH_BASE (CONFIG_SYS_BMAN_MEM_BASE + \ 55 CONFIG_SYS_BMAN_CENA_SIZE) 56 #define CONFIG_SYS_BMAN_CINH_SIZE (CONFIG_SYS_BMAN_MEM_SIZE >> 1) 57 #define CONFIG_SYS_BMAN_SWP_ISDR_REG 0x3E80 58 #define CONFIG_SYS_QMAN_NUM_PORTALS 10 59 #define CONFIG_SYS_QMAN_MEM_BASE 0x500000000 60 #define CONFIG_SYS_QMAN_MEM_PHYS CONFIG_SYS_QMAN_MEM_BASE 61 #define CONFIG_SYS_QMAN_MEM_SIZE 0x08000000 62 #define CONFIG_SYS_QMAN_SP_CENA_SIZE 0x10000 63 #define CONFIG_SYS_QMAN_SP_CINH_SIZE 0x10000 64 #define CONFIG_SYS_QMAN_CENA_BASE CONFIG_SYS_QMAN_MEM_BASE 65 #define CONFIG_SYS_QMAN_CENA_SIZE (CONFIG_SYS_QMAN_MEM_SIZE >> 1) 66 #define CONFIG_SYS_QMAN_CINH_BASE (CONFIG_SYS_QMAN_MEM_BASE + \ 67 CONFIG_SYS_QMAN_CENA_SIZE) 68 #define CONFIG_SYS_QMAN_CINH_SIZE (CONFIG_SYS_QMAN_MEM_SIZE >> 1) 69 #define CONFIG_SYS_QMAN_SWP_ISDR_REG 0x3680 70 71 #define CONFIG_SYS_FSL_TIMER_ADDR 0x02b00000 72 73 #define I2C1_BASE_ADDR (CONFIG_SYS_IMMR + 0x01180000) 74 #define I2C2_BASE_ADDR (CONFIG_SYS_IMMR + 0x01190000) 75 #define I2C3_BASE_ADDR (CONFIG_SYS_IMMR + 0x011a0000) 76 #define I2C4_BASE_ADDR (CONFIG_SYS_IMMR + 0x011b0000) 77 78 #define WDOG1_BASE_ADDR (CONFIG_SYS_IMMR + 0x01ad0000) 79 80 #define QSPI0_BASE_ADDR (CONFIG_SYS_IMMR + 0x00550000) 81 #define DSPI1_BASE_ADDR (CONFIG_SYS_IMMR + 0x01100000) 82 83 #define GPIO1_BASE_ADDR (CONFIG_SYS_IMMR + 0x1300000) 84 #define GPIO2_BASE_ADDR (CONFIG_SYS_IMMR + 0x1310000) 85 #define GPIO3_BASE_ADDR (CONFIG_SYS_IMMR + 0x1320000) 86 #define GPIO4_BASE_ADDR (CONFIG_SYS_IMMR + 0x1330000) 87 88 #define QE_BASE_ADDR (CONFIG_SYS_IMMR + 0x1400000) 89 90 #define LPUART_BASE (CONFIG_SYS_IMMR + 0x01950000) 91 92 #define EDMA_BASE_ADDR (CONFIG_SYS_IMMR + 0x01c00000) 93 94 #define AHCI_BASE_ADDR (CONFIG_SYS_IMMR + 0x02200000) 95 96 #define QDMA_BASE_ADDR (CONFIG_SYS_IMMR + 0x07380000) 97 #define QMAN_CQSIDR_REG 0x20a80 98 99 #define CONFIG_SYS_PCIE1_PHYS_ADDR 0x4000000000ULL 100 #define CONFIG_SYS_PCIE2_PHYS_ADDR 0x4800000000ULL 101 #define CONFIG_SYS_PCIE3_PHYS_ADDR 0x5000000000ULL 102 /* LUT registers */ 103 #ifdef CONFIG_ARCH_LS1012A 104 #define PCIE_LUT_BASE 0xC0000 105 #else 106 #define PCIE_LUT_BASE 0x10000 107 #endif 108 #define PCIE_LUT_LCTRL0 0x7F8 109 #define PCIE_LUT_DBG 0x7FC 110 111 /* TZ Address Space Controller Definitions */ 112 #define TZASC1_BASE 0x01100000 /* as per CCSR map. */ 113 #define TZASC2_BASE 0x01110000 /* as per CCSR map. */ 114 #define TZASC3_BASE 0x01120000 /* as per CCSR map. */ 115 #define TZASC4_BASE 0x01130000 /* as per CCSR map. */ 116 #define TZASC_BUILD_CONFIG_REG(x) ((TZASC1_BASE + (x * 0x10000))) 117 #define TZASC_ACTION_REG(x) ((TZASC1_BASE + (x * 0x10000)) + 0x004) 118 #define TZASC_GATE_KEEPER(x) ((TZASC1_BASE + (x * 0x10000)) + 0x008) 119 #define TZASC_REGION_BASE_LOW_0(x) ((TZASC1_BASE + (x * 0x10000)) + 0x100) 120 #define TZASC_REGION_BASE_HIGH_0(x) ((TZASC1_BASE + (x * 0x10000)) + 0x104) 121 #define TZASC_REGION_TOP_LOW_0(x) ((TZASC1_BASE + (x * 0x10000)) + 0x108) 122 #define TZASC_REGION_TOP_HIGH_0(x) ((TZASC1_BASE + (x * 0x10000)) + 0x10C) 123 #define TZASC_REGION_ATTRIBUTES_0(x) ((TZASC1_BASE + (x * 0x10000)) + 0x110) 124 #define TZASC_REGION_ID_ACCESS_0(x) ((TZASC1_BASE + (x * 0x10000)) + 0x114) 125 126 #define TP_ITYP_AV 0x00000001 /* Initiator available */ 127 #define TP_ITYP_TYPE(x) (((x) & 0x6) >> 1) /* Initiator Type */ 128 #define TP_ITYP_TYPE_ARM 0x0 129 #define TP_ITYP_TYPE_PPC 0x1 /* PowerPC */ 130 #define TP_ITYP_TYPE_OTHER 0x2 /* StarCore DSP */ 131 #define TP_ITYP_TYPE_HA 0x3 /* HW Accelerator */ 132 #define TP_ITYP_THDS(x) (((x) & 0x18) >> 3) /* # threads */ 133 #define TP_ITYP_VER(x) (((x) & 0xe0) >> 5) /* Initiator Version */ 134 #define TY_ITYP_VER_A7 0x1 135 #define TY_ITYP_VER_A53 0x2 136 #define TY_ITYP_VER_A57 0x3 137 #define TY_ITYP_VER_A72 0x4 138 139 #define TP_CLUSTER_EOC 0xc0000000 /* end of clusters */ 140 #define TP_CLUSTER_INIT_MASK 0x0000003f /* initiator mask */ 141 #define TP_INIT_PER_CLUSTER 4 142 143 /* 144 * Define default values for some CCSR macros to make header files cleaner* 145 * 146 * To completely disable CCSR relocation in a board header file, define 147 * CONFIG_SYS_CCSR_DO_NOT_RELOCATE. This will force CONFIG_SYS_CCSRBAR_PHYS 148 * to a value that is the same as CONFIG_SYS_CCSRBAR. 149 */ 150 151 #ifdef CONFIG_SYS_CCSRBAR_PHYS 152 #error "Do not define CONFIG_SYS_CCSRBAR_PHYS directly. Use \ 153 CONFIG_SYS_CCSRBAR_PHYS_LOW and/or CONFIG_SYS_CCSRBAR_PHYS_HIGH instead." 154 #endif 155 156 #ifdef CONFIG_SYS_CCSR_DO_NOT_RELOCATE 157 #undef CONFIG_SYS_CCSRBAR_PHYS_HIGH 158 #undef CONFIG_SYS_CCSRBAR_PHYS_LOW 159 #define CONFIG_SYS_CCSRBAR_PHYS_HIGH 0 160 #endif 161 162 #ifndef CONFIG_SYS_CCSRBAR 163 #define CONFIG_SYS_CCSRBAR 0x01000000 164 #endif 165 166 #ifndef CONFIG_SYS_CCSRBAR_PHYS_HIGH 167 #define CONFIG_SYS_CCSRBAR_PHYS_HIGH 0 168 #endif 169 170 #ifndef CONFIG_SYS_CCSRBAR_PHYS_LOW 171 #define CONFIG_SYS_CCSRBAR_PHYS_LOW 0x01000000 172 #endif 173 174 #define CONFIG_SYS_CCSRBAR_PHYS ((CONFIG_SYS_CCSRBAR_PHYS_HIGH * 1ull) << 32 | \ 175 CONFIG_SYS_CCSRBAR_PHYS_LOW) 176 177 struct sys_info { 178 unsigned long freq_processor[CONFIG_MAX_CPUS]; 179 /* frequency of platform PLL */ 180 unsigned long freq_systembus; 181 unsigned long freq_ddrbus; 182 unsigned long freq_localbus; 183 unsigned long freq_cga_m2; 184 #ifdef CONFIG_SYS_DPAA_FMAN 185 unsigned long freq_fman[CONFIG_SYS_NUM_FMAN]; 186 #endif 187 unsigned long freq_qman; 188 }; 189 190 #define CONFIG_SYS_FSL_FM1_OFFSET 0xa00000 191 #define CONFIG_SYS_FSL_FM1_RX0_1G_OFFSET 0xa88000 192 #define CONFIG_SYS_FSL_FM1_RX1_1G_OFFSET 0xa89000 193 #define CONFIG_SYS_FSL_FM1_RX2_1G_OFFSET 0xa8a000 194 #define CONFIG_SYS_FSL_FM1_RX3_1G_OFFSET 0xa8b000 195 #define CONFIG_SYS_FSL_FM1_RX4_1G_OFFSET 0xa8c000 196 #define CONFIG_SYS_FSL_FM1_RX5_1G_OFFSET 0xa8d000 197 198 #define CONFIG_SYS_FSL_FM1_DTSEC1_OFFSET 0xae0000 199 #define CONFIG_SYS_FSL_FM1_ADDR \ 200 (CONFIG_SYS_IMMR + CONFIG_SYS_FSL_FM1_OFFSET) 201 #define CONFIG_SYS_FSL_FM1_DTSEC1_ADDR \ 202 (CONFIG_SYS_IMMR + CONFIG_SYS_FSL_FM1_DTSEC1_OFFSET) 203 204 #define CONFIG_SYS_FSL_SEC_OFFSET 0x700000ull 205 #define CONFIG_SYS_FSL_JR0_OFFSET 0x710000ull 206 #define FSL_SEC_JR0_OFFSET CONFIG_SYS_FSL_JR0_OFFSET 207 #define FSL_SEC_JR1_OFFSET 0x720000ull 208 #define FSL_SEC_JR2_OFFSET 0x730000ull 209 #define FSL_SEC_JR3_OFFSET 0x740000ull 210 #define CONFIG_SYS_FSL_SEC_ADDR \ 211 (CONFIG_SYS_IMMR + CONFIG_SYS_FSL_SEC_OFFSET) 212 #define CONFIG_SYS_FSL_JR0_ADDR \ 213 (CONFIG_SYS_IMMR + CONFIG_SYS_FSL_JR0_OFFSET) 214 #define FSL_SEC_JR0_BASE_ADDR (CONFIG_SYS_IMMR + FSL_SEC_JR0_OFFSET) 215 #define FSL_SEC_JR1_BASE_ADDR (CONFIG_SYS_IMMR + FSL_SEC_JR1_OFFSET) 216 #define FSL_SEC_JR2_BASE_ADDR (CONFIG_SYS_IMMR + FSL_SEC_JR2_OFFSET) 217 #define FSL_SEC_JR3_BASE_ADDR (CONFIG_SYS_IMMR + FSL_SEC_JR3_OFFSET) 218 219 /* Device Configuration and Pin Control */ 220 #define DCFG_DCSR_PORCR1 0x0 221 #define DCFG_DCSR_ECCCR2 0x524 222 #define DISABLE_PFE_ECC BIT(13) 223 224 struct ccsr_gur { 225 u32 porsr1; /* POR status 1 */ 226 #define FSL_CHASSIS2_CCSR_PORSR1_RCW_MASK 0xFF800000 227 u32 porsr2; /* POR status 2 */ 228 u8 res_008[0x20-0x8]; 229 u32 gpporcr1; /* General-purpose POR configuration */ 230 u32 gpporcr2; 231 #define FSL_CHASSIS2_DCFG_FUSESR_VID_SHIFT 25 232 #define FSL_CHASSIS2_DCFG_FUSESR_VID_MASK 0x1F 233 #define FSL_CHASSIS2_DCFG_FUSESR_ALTVID_SHIFT 20 234 #define FSL_CHASSIS2_DCFG_FUSESR_ALTVID_MASK 0x1F 235 u32 dcfg_fusesr; /* Fuse status register */ 236 u8 res_02c[0x70-0x2c]; 237 u32 devdisr; /* Device disable control */ 238 #define FSL_CHASSIS2_DEVDISR2_DTSEC1_1 0x80000000 239 #define FSL_CHASSIS2_DEVDISR2_DTSEC1_2 0x40000000 240 #define FSL_CHASSIS2_DEVDISR2_DTSEC1_3 0x20000000 241 #define FSL_CHASSIS2_DEVDISR2_DTSEC1_4 0x10000000 242 #define FSL_CHASSIS2_DEVDISR2_DTSEC1_5 0x08000000 243 #define FSL_CHASSIS2_DEVDISR2_DTSEC1_6 0x04000000 244 #define FSL_CHASSIS2_DEVDISR2_DTSEC1_9 0x00800000 245 #define FSL_CHASSIS2_DEVDISR2_DTSEC1_10 0x00400000 246 #define FSL_CHASSIS2_DEVDISR2_10GEC1_1 0x00800000 247 #define FSL_CHASSIS2_DEVDISR2_10GEC1_2 0x00400000 248 #define FSL_CHASSIS2_DEVDISR2_10GEC1_3 0x80000000 249 #define FSL_CHASSIS2_DEVDISR2_10GEC1_4 0x40000000 250 u32 devdisr2; /* Device disable control 2 */ 251 u32 devdisr3; /* Device disable control 3 */ 252 u32 devdisr4; /* Device disable control 4 */ 253 u32 devdisr5; /* Device disable control 5 */ 254 u32 devdisr6; /* Device disable control 6 */ 255 u32 devdisr7; /* Device disable control 7 */ 256 u8 res_08c[0x94-0x8c]; 257 u32 coredisru; /* uppper portion for support of 64 cores */ 258 u32 coredisrl; /* lower portion for support of 64 cores */ 259 u8 res_09c[0xa0-0x9c]; 260 u32 pvr; /* Processor version */ 261 u32 svr; /* System version */ 262 u32 mvr; /* Manufacturing version */ 263 u8 res_0ac[0xb0-0xac]; 264 u32 rstcr; /* Reset control */ 265 u32 rstrqpblsr; /* Reset request preboot loader status */ 266 u8 res_0b8[0xc0-0xb8]; 267 u32 rstrqmr1; /* Reset request mask */ 268 u8 res_0c4[0xc8-0xc4]; 269 u32 rstrqsr1; /* Reset request status */ 270 u8 res_0cc[0xd4-0xcc]; 271 u32 rstrqwdtmrl; /* Reset request WDT mask */ 272 u8 res_0d8[0xdc-0xd8]; 273 u32 rstrqwdtsrl; /* Reset request WDT status */ 274 u8 res_0e0[0xe4-0xe0]; 275 u32 brrl; /* Boot release */ 276 u8 res_0e8[0x100-0xe8]; 277 u32 rcwsr[16]; /* Reset control word status */ 278 #define FSL_CHASSIS2_RCWSR0_SYS_PLL_RAT_SHIFT 25 279 #define FSL_CHASSIS2_RCWSR0_SYS_PLL_RAT_MASK 0x1f 280 #define FSL_CHASSIS2_RCWSR0_MEM_PLL_RAT_SHIFT 16 281 #define FSL_CHASSIS2_RCWSR0_MEM_PLL_RAT_MASK 0x3f 282 #define FSL_CHASSIS2_RCWSR4_SRDS1_PRTCL_MASK 0xffff0000 283 #define FSL_CHASSIS2_RCWSR4_SRDS1_PRTCL_SHIFT 16 284 #define FSL_CHASSIS2_RCWSR4_SRDS2_PRTCL_MASK 0x0000ffff 285 #define FSL_CHASSIS2_RCWSR4_SRDS2_PRTCL_SHIFT 0 286 #define RCW_SB_EN_REG_INDEX 7 287 #define RCW_SB_EN_MASK 0x00200000 288 289 u8 res_140[0x200-0x140]; 290 u32 scratchrw[4]; /* Scratch Read/Write */ 291 u8 res_210[0x300-0x210]; 292 u32 scratchw1r[4]; /* Scratch Read (Write once) */ 293 u8 res_310[0x400-0x310]; 294 u32 crstsr[12]; 295 u8 res_430[0x500-0x430]; 296 297 /* PCI Express n Logical I/O Device Number register */ 298 u32 dcfg_ccsr_pex1liodnr; 299 u32 dcfg_ccsr_pex2liodnr; 300 u32 dcfg_ccsr_pex3liodnr; 301 u32 dcfg_ccsr_pex4liodnr; 302 /* RIO n Logical I/O Device Number register */ 303 u32 dcfg_ccsr_rio1liodnr; 304 u32 dcfg_ccsr_rio2liodnr; 305 u32 dcfg_ccsr_rio3liodnr; 306 u32 dcfg_ccsr_rio4liodnr; 307 /* USB Logical I/O Device Number register */ 308 u32 dcfg_ccsr_usb1liodnr; 309 u32 dcfg_ccsr_usb2liodnr; 310 u32 dcfg_ccsr_usb3liodnr; 311 u32 dcfg_ccsr_usb4liodnr; 312 /* SD/MMC Logical I/O Device Number register */ 313 u32 dcfg_ccsr_sdmmc1liodnr; 314 u32 dcfg_ccsr_sdmmc2liodnr; 315 u32 dcfg_ccsr_sdmmc3liodnr; 316 u32 dcfg_ccsr_sdmmc4liodnr; 317 /* RIO Message Unit Logical I/O Device Number register */ 318 u32 dcfg_ccsr_riomaintliodnr; 319 320 u8 res_544[0x550-0x544]; 321 u32 sataliodnr[4]; 322 u8 res_560[0x570-0x560]; 323 324 u32 dcfg_ccsr_misc1liodnr; 325 u32 dcfg_ccsr_misc2liodnr; 326 u32 dcfg_ccsr_misc3liodnr; 327 u32 dcfg_ccsr_misc4liodnr; 328 u32 dcfg_ccsr_dma1liodnr; 329 u32 dcfg_ccsr_dma2liodnr; 330 u32 dcfg_ccsr_dma3liodnr; 331 u32 dcfg_ccsr_dma4liodnr; 332 u32 dcfg_ccsr_spare1liodnr; 333 u32 dcfg_ccsr_spare2liodnr; 334 u32 dcfg_ccsr_spare3liodnr; 335 u32 dcfg_ccsr_spare4liodnr; 336 u8 res_5a0[0x600-0x5a0]; 337 u32 dcfg_ccsr_pblsr; 338 339 u32 pamubypenr; 340 u32 dmacr1; 341 342 u8 res_60c[0x610-0x60c]; 343 u32 dcfg_ccsr_gensr1; 344 u32 dcfg_ccsr_gensr2; 345 u32 dcfg_ccsr_gensr3; 346 u32 dcfg_ccsr_gensr4; 347 u32 dcfg_ccsr_gencr1; 348 u32 dcfg_ccsr_gencr2; 349 u32 dcfg_ccsr_gencr3; 350 u32 dcfg_ccsr_gencr4; 351 u32 dcfg_ccsr_gencr5; 352 u32 dcfg_ccsr_gencr6; 353 u32 dcfg_ccsr_gencr7; 354 u8 res_63c[0x658-0x63c]; 355 u32 dcfg_ccsr_cgensr1; 356 u32 dcfg_ccsr_cgensr0; 357 u8 res_660[0x678-0x660]; 358 u32 dcfg_ccsr_cgencr1; 359 360 u32 dcfg_ccsr_cgencr0; 361 u8 res_680[0x700-0x680]; 362 u32 dcfg_ccsr_sriopstecr; 363 u32 dcfg_ccsr_dcsrcr; 364 365 u8 res_708[0x740-0x708]; /* add more registers when needed */ 366 u32 tp_ityp[64]; /* Topology Initiator Type Register */ 367 struct { 368 u32 upper; 369 u32 lower; 370 } tp_cluster[16]; 371 u8 res_8c0[0xa00-0x8c0]; /* add more registers when needed */ 372 u32 dcfg_ccsr_qmbm_warmrst; 373 u8 res_a04[0xa20-0xa04]; /* add more registers when needed */ 374 u32 dcfg_ccsr_reserved0; 375 u32 dcfg_ccsr_reserved1; 376 }; 377 378 #define SCFG_QSPI_CLKSEL 0x40100000 379 #define SCFG_USBDRVVBUS_SELCR_USB1 0x00000000 380 #define SCFG_USBDRVVBUS_SELCR_USB2 0x00000001 381 #define SCFG_USBDRVVBUS_SELCR_USB3 0x00000002 382 #define SCFG_USBPWRFAULT_INACTIVE 0x00000000 383 #define SCFG_USBPWRFAULT_SHARED 0x00000001 384 #define SCFG_USBPWRFAULT_DEDICATED 0x00000002 385 #define SCFG_USBPWRFAULT_USB3_SHIFT 4 386 #define SCFG_USBPWRFAULT_USB2_SHIFT 2 387 #define SCFG_USBPWRFAULT_USB1_SHIFT 0 388 389 #define SCFG_BASE 0x01570000 390 #define SCFG_USB3PRM1CR_USB1 0x070 391 #define SCFG_USB3PRM2CR_USB1 0x074 392 #define SCFG_USB3PRM1CR_USB2 0x07C 393 #define SCFG_USB3PRM2CR_USB2 0x080 394 #define SCFG_USB3PRM1CR_USB3 0x088 395 #define SCFG_USB3PRM2CR_USB3 0x08c 396 #define SCFG_USB_TXVREFTUNE 0x9 397 #define SCFG_USB_SQRXTUNE_MASK 0x7 398 #define SCFG_USB_PCSTXSWINGFULL 0x47 399 #define SCFG_USB_PHY1 0x084F0000 400 #define SCFG_USB_PHY2 0x08500000 401 #define SCFG_USB_PHY3 0x08510000 402 #define SCFG_USB_PHY_RX_OVRD_IN_HI 0x200c 403 #define USB_PHY_RX_EQ_VAL_1 0x0000 404 #define USB_PHY_RX_EQ_VAL_2 0x0080 405 #define USB_PHY_RX_EQ_VAL_3 0x0380 406 #define USB_PHY_RX_EQ_VAL_4 0x0b80 407 408 #define SCFG_SNPCNFGCR_SECRDSNP 0x80000000 409 #define SCFG_SNPCNFGCR_SECWRSNP 0x40000000 410 #define SCFG_SNPCNFGCR_SATARDSNP 0x00800000 411 #define SCFG_SNPCNFGCR_SATAWRSNP 0x00400000 412 #define SCFG_SNPCNFGCR_USB1RDSNP 0x00200000 413 #define SCFG_SNPCNFGCR_USB1WRSNP 0x00100000 414 #define SCFG_SNPCNFGCR_USB2RDSNP 0x00008000 415 #define SCFG_SNPCNFGCR_USB2WRSNP 0x00010000 416 #define SCFG_SNPCNFGCR_USB3RDSNP 0x00002000 417 #define SCFG_SNPCNFGCR_USB3WRSNP 0x00004000 418 419 /* RGMIIPCR bit definitions*/ 420 #define SCFG_RGMIIPCR_EN_AUTO BIT(3) 421 #define SCFG_RGMIIPCR_SETSP_1000M BIT(2) 422 #define SCFG_RGMIIPCR_SETSP_100M 0 423 #define SCFG_RGMIIPCR_SETSP_10M BIT(1) 424 #define SCFG_RGMIIPCR_SETFD BIT(0) 425 426 /* PFEASBCR bit definitions */ 427 #define SCFG_PFEASBCR_ARCACHE0 BIT(31) 428 #define SCFG_PFEASBCR_AWCACHE0 BIT(30) 429 #define SCFG_PFEASBCR_ARCACHE1 BIT(29) 430 #define SCFG_PFEASBCR_AWCACHE1 BIT(28) 431 #define SCFG_PFEASBCR_ARSNP BIT(27) 432 #define SCFG_PFEASBCR_AWSNP BIT(26) 433 434 /* WR_QoS1 PFE bit definitions */ 435 #define SCFG_WR_QOS1_PFE1_QOS GENMASK(27, 24) 436 #define SCFG_WR_QOS1_PFE2_QOS GENMASK(23, 20) 437 438 /* RD_QoS1 PFE bit definitions */ 439 #define SCFG_RD_QOS1_PFE1_QOS GENMASK(27, 24) 440 #define SCFG_RD_QOS1_PFE2_QOS GENMASK(23, 20) 441 442 /* Supplemental Configuration Unit */ 443 struct ccsr_scfg { 444 u8 res_000[0x100-0x000]; 445 u32 usb2_icid; 446 u32 usb3_icid; 447 u8 res_108[0x114-0x108]; 448 u32 dma_icid; 449 u32 sata_icid; 450 u32 usb1_icid; 451 u32 qe_icid; 452 u32 sdhc_icid; 453 u32 edma_icid; 454 u32 etr_icid; 455 u32 core_sft_rst[4]; 456 u8 res_140[0x158-0x140]; 457 u32 altcbar; 458 u32 qspi_cfg; 459 u8 res_160[0x164 - 0x160]; 460 u32 wr_qos1; 461 u32 wr_qos2; 462 u32 rd_qos1; 463 u32 rd_qos2; 464 u8 res_174[0x180 - 0x174]; 465 u32 dmamcr; 466 u8 res_184[0x188-0x184]; 467 u32 gic_align; 468 u32 debug_icid; 469 u8 res_190[0x1a4-0x190]; 470 u32 snpcnfgcr; 471 u8 res_1a8[0x1ac-0x1a8]; 472 u32 intpcr; 473 u8 res_1b0[0x204-0x1b0]; 474 u32 coresrencr; 475 u8 res_208[0x220-0x208]; 476 u32 rvbar0_0; 477 u32 rvbar0_1; 478 u32 rvbar1_0; 479 u32 rvbar1_1; 480 u32 rvbar2_0; 481 u32 rvbar2_1; 482 u32 rvbar3_0; 483 u32 rvbar3_1; 484 u32 lpmcsr; 485 u8 res_244[0x400-0x244]; 486 u32 qspidqscr; 487 u32 ecgtxcmcr; 488 u32 sdhciovselcr; 489 u32 rcwpmuxcr0; 490 u32 usbdrvvbus_selcr; 491 u32 usbpwrfault_selcr; 492 u32 usb_refclk_selcr1; 493 u32 usb_refclk_selcr2; 494 u32 usb_refclk_selcr3; 495 u8 res_424[0x434 - 0x424]; 496 u32 rgmiipcr; 497 u32 res_438; 498 u32 rgmiipsr; 499 u32 pfepfcssr1; 500 u32 pfeintencr1; 501 u32 pfepfcssr2; 502 u32 pfeintencr2; 503 u32 pfeerrcr; 504 u32 pfeeerrintencr; 505 u32 pfeasbcr; 506 u32 pfebsbcr; 507 u8 res_460[0x484 - 0x460]; 508 u32 mdioselcr; 509 u8 res_468[0x600 - 0x488]; 510 u32 scratchrw[4]; 511 u8 res_610[0x680-0x610]; 512 u32 corebcr; 513 u8 res_684[0x1000-0x684]; 514 u32 pex1msiir; 515 u32 pex1msir; 516 u8 res_1008[0x2000-0x1008]; 517 u32 pex2; 518 u32 pex2msir; 519 u8 res_2008[0x3000-0x2008]; 520 u32 pex3msiir; 521 u32 pex3msir; 522 }; 523 524 /* Clocking */ 525 struct ccsr_clk { 526 struct { 527 u32 clkcncsr; /* core cluster n clock control status */ 528 u8 res_004[0x0c]; 529 u32 clkcghwacsr; /* Clock generator n hardware accelerator */ 530 u8 res_014[0x0c]; 531 } clkcsr[4]; 532 u8 res_040[0x780]; /* 0x100 */ 533 struct { 534 u32 pllcngsr; 535 u8 res_804[0x1c]; 536 } pllcgsr[2]; 537 u8 res_840[0x1c0]; 538 u32 clkpcsr; /* 0xa00 Platform clock domain control/status */ 539 u8 res_a04[0x1fc]; 540 u32 pllpgsr; /* 0xc00 Platform PLL General Status */ 541 u8 res_c04[0x1c]; 542 u32 plldgsr; /* 0xc20 DDR PLL General Status */ 543 u8 res_c24[0x3dc]; 544 }; 545 546 /* System Counter */ 547 struct sctr_regs { 548 u32 cntcr; 549 u32 cntsr; 550 u32 cntcv1; 551 u32 cntcv2; 552 u32 resv1[4]; 553 u32 cntfid0; 554 u32 cntfid1; 555 u32 resv2[1002]; 556 u32 counterid[12]; 557 }; 558 559 #define SRDS_MAX_LANES 4 560 struct ccsr_serdes { 561 struct { 562 u32 rstctl; /* Reset Control Register */ 563 #define SRDS_RSTCTL_RST 0x80000000 564 #define SRDS_RSTCTL_RSTDONE 0x40000000 565 #define SRDS_RSTCTL_RSTERR 0x20000000 566 #define SRDS_RSTCTL_SWRST 0x10000000 567 #define SRDS_RSTCTL_SDEN 0x00000020 568 #define SRDS_RSTCTL_SDRST_B 0x00000040 569 #define SRDS_RSTCTL_PLLRST_B 0x00000080 570 u32 pllcr0; /* PLL Control Register 0 */ 571 #define SRDS_PLLCR0_POFF 0x80000000 572 #define SRDS_PLLCR0_RFCK_SEL_MASK 0x70000000 573 #define SRDS_PLLCR0_RFCK_SEL_100 0x00000000 574 #define SRDS_PLLCR0_RFCK_SEL_125 0x10000000 575 #define SRDS_PLLCR0_RFCK_SEL_156_25 0x20000000 576 #define SRDS_PLLCR0_RFCK_SEL_150 0x30000000 577 #define SRDS_PLLCR0_RFCK_SEL_161_13 0x40000000 578 #define SRDS_PLLCR0_RFCK_SEL_122_88 0x50000000 579 #define SRDS_PLLCR0_PLL_LCK 0x00800000 580 #define SRDS_PLLCR0_FRATE_SEL_MASK 0x000f0000 581 #define SRDS_PLLCR0_FRATE_SEL_5 0x00000000 582 #define SRDS_PLLCR0_FRATE_SEL_3_75 0x00050000 583 #define SRDS_PLLCR0_FRATE_SEL_5_15 0x00060000 584 #define SRDS_PLLCR0_FRATE_SEL_4 0x00070000 585 #define SRDS_PLLCR0_FRATE_SEL_3_12 0x00090000 586 #define SRDS_PLLCR0_FRATE_SEL_3 0x000a0000 587 u32 pllcr1; /* PLL Control Register 1 */ 588 #define SRDS_PLLCR1_PLL_BWSEL 0x08000000 589 u32 res_0c; /* 0x00c */ 590 u32 pllcr3; 591 u32 pllcr4; 592 u32 pllcr5; /* 0x018 SerDes PLL1 Control 5 */ 593 u8 res_1c[0x20-0x1c]; 594 } bank[2]; 595 u8 res_40[0x90-0x40]; 596 u32 srdstcalcr; /* 0x90 TX Calibration Control */ 597 u8 res_94[0xa0-0x94]; 598 u32 srdsrcalcr; /* 0xa0 RX Calibration Control */ 599 u8 res_a4[0xb0-0xa4]; 600 u32 srdsgr0; /* 0xb0 General Register 0 */ 601 u8 res_b4[0x100-0xb4]; 602 struct { 603 u32 lnpssr0; /* 0x100, 0x120, 0x140, 0x160 */ 604 u8 res_104[0x120-0x104]; 605 } lnpssr[4]; /* Lane A, B, C, D */ 606 u8 res_180[0x200-0x180]; 607 u32 srdspccr0; /* 0x200 Protocol Configuration 0 */ 608 u32 srdspccr1; /* 0x204 Protocol Configuration 1 */ 609 u32 srdspccr2; /* 0x208 Protocol Configuration 2 */ 610 u32 srdspccr3; /* 0x20c Protocol Configuration 3 */ 611 u32 srdspccr4; /* 0x210 Protocol Configuration 4 */ 612 u32 srdspccr5; /* 0x214 Protocol Configuration 5 */ 613 u32 srdspccr6; /* 0x218 Protocol Configuration 6 */ 614 u32 srdspccr7; /* 0x21c Protocol Configuration 7 */ 615 u32 srdspccr8; /* 0x220 Protocol Configuration 8 */ 616 u32 srdspccr9; /* 0x224 Protocol Configuration 9 */ 617 u32 srdspccra; /* 0x228 Protocol Configuration A */ 618 u32 srdspccrb; /* 0x22c Protocol Configuration B */ 619 u8 res_230[0x800-0x230]; 620 struct { 621 u32 gcr0; /* 0x800 General Control Register 0 */ 622 u32 gcr1; /* 0x804 General Control Register 1 */ 623 u32 gcr2; /* 0x808 General Control Register 2 */ 624 u32 sscr0; 625 u32 recr0; /* 0x810 Receive Equalization Control */ 626 u32 recr1; 627 u32 tecr0; /* 0x818 Transmit Equalization Control */ 628 u32 sscr1; 629 u32 ttlcr0; /* 0x820 Transition Tracking Loop Ctrl 0 */ 630 u8 res_824[0x83c-0x824]; 631 u32 tcsr3; 632 } lane[4]; /* Lane A, B, C, D */ 633 u8 res_900[0x1000-0x900]; /* from 0x900 to 0xfff */ 634 struct { 635 u32 srdspexcr0; /* 0x1000, 0x1040, 0x1080 */ 636 u8 res_1004[0x1040-0x1004]; 637 } pcie[3]; 638 u8 res_10c0[0x1800-0x10c0]; 639 struct { 640 u8 res_1800[0x1804-0x1800]; 641 u32 srdssgmiicr1; /* 0x1804 SGMII Protocol Control 1 */ 642 u8 res_1808[0x180c-0x1808]; 643 u32 srdssgmiicr3; /* 0x180c SGMII Protocol Control 3 */ 644 } sgmii[4]; /* Lane A, B, C, D */ 645 u8 res_1840[0x1880-0x1840]; 646 struct { 647 u8 res_1880[0x1884-0x1880]; 648 u32 srdsqsgmiicr1; /* 0x1884 QSGMII Protocol Control 1 */ 649 u8 res_1888[0x188c-0x1888]; 650 u32 srdsqsgmiicr3; /* 0x188c QSGMII Protocol Control 3 */ 651 } qsgmii[2]; /* Lane A, B */ 652 u8 res_18a0[0x1980-0x18a0]; 653 struct { 654 u8 res_1980[0x1984-0x1980]; 655 u32 srdsxficr1; /* 0x1984 XFI Protocol Control 1 */ 656 u8 res_1988[0x198c-0x1988]; 657 u32 srdsxficr3; /* 0x198c XFI Protocol Control 3 */ 658 } xfi[2]; /* Lane A, B */ 659 u8 res_19a0[0x2000-0x19a0]; /* from 0x19a0 to 0x1fff */ 660 }; 661 662 struct ccsr_gpio { 663 u32 gpdir; 664 u32 gpodr; 665 u32 gpdat; 666 u32 gpier; 667 u32 gpimr; 668 u32 gpicr; 669 u32 gpibe; 670 }; 671 672 /* MMU 500 */ 673 #define SMMU_SCR0 (SMMU_BASE + 0x0) 674 #define SMMU_SCR1 (SMMU_BASE + 0x4) 675 #define SMMU_SCR2 (SMMU_BASE + 0x8) 676 #define SMMU_SACR (SMMU_BASE + 0x10) 677 #define SMMU_IDR0 (SMMU_BASE + 0x20) 678 #define SMMU_IDR1 (SMMU_BASE + 0x24) 679 680 #define SMMU_NSCR0 (SMMU_BASE + 0x400) 681 #define SMMU_NSCR2 (SMMU_BASE + 0x408) 682 #define SMMU_NSACR (SMMU_BASE + 0x410) 683 684 #define SCR0_CLIENTPD_MASK 0x00000001 685 #define SCR0_USFCFG_MASK 0x00000400 686 687 #ifdef CONFIG_TFABOOT 688 #define RCW_SRC_MASK (0xFF800000) 689 #define RCW_SRC_BIT 23 690 691 /* RCW SRC NAND */ 692 #define RCW_SRC_NAND_MASK (0x100) 693 #define RCW_SRC_NAND_VAL (0x100) 694 #define NAND_RESERVED_MASK (0xFC) 695 #define NAND_RESERVED_1 (0x0) 696 #define NAND_RESERVED_2 (0x80) 697 698 /* RCW SRC NOR */ 699 #define RCW_SRC_NOR_MASK (0x1F0) 700 #define NOR_8B_VAL (0x10) 701 #define NOR_16B_VAL (0x20) 702 #define SD_VAL (0x40) 703 #define QSPI_VAL1 (0x44) 704 #define QSPI_VAL2 (0x45) 705 #endif 706 707 uint get_svr(void); 708 709 #endif /* __ARCH_FSL_LSCH2_IMMAP_H__*/ 710