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Searched refs:rsrc2 (Results 1 – 9 of 9) sorted by relevance

/external/mesa3d/src/amd/common/
Dac_binary.c68 conf->rsrc2 = value; in ac_parse_shader_binary_config()
72 conf->rsrc2 = value; in ac_parse_shader_binary_config()
76 conf->rsrc2 = value; in ac_parse_shader_binary_config()
80 conf->rsrc2 = value; in ac_parse_shader_binary_config()
84 conf->rsrc2 = value; in ac_parse_shader_binary_config()
Dac_binary.h49 unsigned rsrc2; member
Dac_rtld.c547 assert(config->rsrc1 == 0 && config->rsrc2 == 0); in ac_rtld_read_config()
549 config->rsrc2 = c.rsrc2; in ac_rtld_read_config()
/external/mesa3d/src/amd/vulkan/
Dradv_shader.c894 config_out->rsrc2 = S_00B12C_USER_SGPR(info->num_user_sgprs) | in radv_postprocess_config()
906 config_out->rsrc2 |= S_00B12C_SO_BASE0_EN(!!info->so.strides[0]) | in radv_postprocess_config()
919 config_out->rsrc2 |= S_00B22C_USER_SGPR_MSB_GFX10(info->num_user_sgprs >> 5); in radv_postprocess_config()
922 config_out->rsrc2 |= S_00B22C_USER_SGPR_MSB_GFX9(info->num_user_sgprs >> 5); in radv_postprocess_config()
929 config_out->rsrc2 |= S_00B22C_OC_LDS_EN(1) | in radv_postprocess_config()
935 config_out->rsrc2 |= S_00B12C_OC_LDS_EN(1) | in radv_postprocess_config()
942 config_out->rsrc2 |= S_00B12C_OC_LDS_EN(1) | in radv_postprocess_config()
945 config_out->rsrc2 |= S_00B22C_SHARED_VGPR_CNT(num_shared_vgpr_blocks); in radv_postprocess_config()
955 config_out->rsrc2 |= S_00B42C_LDS_SIZE_GFX10(info->tcs.num_lds_blocks) | in radv_postprocess_config()
959 config_out->rsrc2 |= S_00B42C_LDS_SIZE_GFX9(info->tcs.num_lds_blocks) | in radv_postprocess_config()
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Dradv_pipeline.c4198 radeon_emit(cs, shader->config.rsrc2); in radv_pipeline_generate_hw_vs()
4261 radeon_emit(cs, shader->config.rsrc2); in radv_pipeline_generate_hw_es()
4271 uint32_t rsrc2 = shader->config.rsrc2; in radv_pipeline_generate_hw_ls() local
4277 rsrc2 |= S_00B52C_LDS_SIZE(num_lds_blocks); in radv_pipeline_generate_hw_ls()
4280 radeon_set_sh_reg(cs, R_00B52C_SPI_SHADER_PGM_RSRC2_LS, rsrc2); in radv_pipeline_generate_hw_ls()
4284 radeon_emit(cs, rsrc2); in radv_pipeline_generate_hw_ls()
4305 radeon_emit(cs, shader->config.rsrc2); in radv_pipeline_generate_hw_ngg()
4442 radeon_emit(cs, shader->config.rsrc2); in radv_pipeline_generate_hw_hs()
4448 radeon_emit(cs, shader->config.rsrc2); in radv_pipeline_generate_hw_hs()
4649 radeon_emit(cs, gs->config.rsrc2 | S_00B22C_LDS_SIZE(gs_state->lds_size)); in radv_pipeline_generate_hw_gs()
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/external/mesa3d/src/gallium/drivers/radeonsi/
Dsi_compute.c98 uint32_t rsrc2 = code_object->compute_pgm_resource_registers >> 32; in code_object_to_config() local
103 out_config->lds_size = MAX2(out_config->lds_size, G_00B84C_LDS_SIZE(rsrc2)); in code_object_to_config()
104 out_config->rsrc2 = rsrc2; in code_object_to_config()
203 shader->config.rsrc2 = S_00B84C_USER_SGPR(user_sgprs) | S_00B84C_SCRATCH_EN(scratch_enabled) | in si_create_compute_state_async()
480 config->rsrc2 &= C_00B84C_LDS_SIZE; in si_switch_compute_shader()
481 config->rsrc2 |= S_00B84C_LDS_SIZE(lds_blocks); in si_switch_compute_shader()
514 radeon_emit(cs, config->rsrc2); in si_switch_compute_shader()
519 config->rsrc1, config->rsrc2); in si_switch_compute_shader()
Dsi_state_shaders.c501 shader->config.rsrc2 = in si_shader_ls()
528 shader->config.rsrc2 = S_00B42C_USER_SGPR(num_user_sgprs) | in si_shader_hs()
532 shader->config.rsrc2 |= S_00B42C_USER_SGPR_MSB_GFX10(num_user_sgprs >> 5); in si_shader_hs()
534 shader->config.rsrc2 |= S_00B42C_USER_SGPR_MSB_GFX9(num_user_sgprs >> 5); in si_shader_hs()
539 shader->config.rsrc2 = S_00B42C_USER_SGPR(GFX6_TCS_NUM_USER_SGPR) | S_00B42C_OC_LDS_EN(1) | in si_shader_hs()
556 si_pm4_set_reg(pm4, R_00B42C_SPI_SHADER_PGM_RSRC2_HS, shader->config.rsrc2); in si_shader_hs()
873 uint32_t rsrc2 = S_00B22C_USER_SGPR(num_user_sgprs) | in si_shader_gs() local
880 rsrc2 |= S_00B22C_USER_SGPR_MSB_GFX10(num_user_sgprs >> 5); in si_shader_gs()
883 rsrc2 |= S_00B22C_USER_SGPR_MSB_GFX9(num_user_sgprs >> 5); in si_shader_gs()
887 si_pm4_set_reg(pm4, R_00B22C_SPI_SHADER_PGM_RSRC2_GS, rsrc2); in si_shader_gs()
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Dsi_state_draw.c250 unsigned hs_rsrc2 = ls_current->config.rsrc2; in si_emit_derived_tess_state()
266 unsigned ls_rsrc2 = ls_current->config.rsrc2; in si_emit_derived_tess_state()
/external/libxaac/decoder/
Dixheaacd_basic_ops.c82 WORD32 *rsrc2 = src2 + vlen - 1; in ixheaacd_windowing_long1() local
92 ixheaacd_mult32_sh1(*rsrc2, *win_fwd)); in ixheaacd_windowing_long1()
98 rsrc2--; in ixheaacd_windowing_long1()
110 ((ixheaacd_mult32_sh1(*rsrc2, *win_fwd)) >> (shift2 - shift1))); in ixheaacd_windowing_long1()
115 rsrc2--; in ixheaacd_windowing_long1()