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/external/swiftshader/third_party/subzero/tests_lit/assembler/arm32/
Dvmov-f2i.ll7 ; RUN: --reg-use=s20,r5,r6 | FileCheck %s --check-prefix=ASM
11 ; RUN: --args -Om1 --reg-use=s20,r5,r6 | FileCheck %s --check-prefix=DIS
15 ; RUN: --reg-use=s20,r5,r6 \
20 ; RUN: --args -Om1 --reg-use=s20,r5,r6 | FileCheck %s --check-prefix=DIS
28 ; ASM: vmov r5, s20
41 ; ASM: vmov r5, s20
54 ; ASM: vmov r5, s20
67 ; ASM: vmov r5, s20
80 ; ASM: vmov s20, r5
93 ; ASM: vmov s20, r5
[all …]
Dvcvt.f32.u32.ll7 ; RUN: --reg-use=s20 | FileCheck %s --check-prefix=ASM
11 ; RUN: --args -Om1 --reg-use=s20 | FileCheck %s --check-prefix=DIS
15 ; RUN: --reg-use=s20 \
20 ; RUN: --args -Om1 --reg-use=s20 | FileCheck %s --check-prefix=DIS
33 ; ASM: vcvt.f32.u32 s20, s20
Dvcvt.u32.f32.ll7 ; RUN: --reg-use=s20 | FileCheck %s --check-prefix=ASM
11 ; RUN: --args -Om1 --reg-use=s20 | FileCheck %s --check-prefix=DIS
15 ; RUN: --reg-use=s20 \
20 ; RUN: --args -Om1 --reg-use=s20 | FileCheck %s --check-prefix=DIS
32 ; ASM: vcvt.u32.f32 s20, s20
Dvcvt.s32.f32.ll7 ; RUN: --reg-use=s20 | FileCheck %s --check-prefix=ASM
11 ; RUN: --args -Om1 --reg-use=s20 | FileCheck %s --check-prefix=DIS
15 ; RUN: --reg-use=s20 \
20 ; RUN: --args -Om1 --reg-use=s20 | FileCheck %s --check-prefix=DIS
33 ; ASM: vcvt.s32.f32 s20, s20
Dvcvt.f32.s32.ll7 ; RUN: --reg-use=s20 | FileCheck %s --check-prefix=ASM
11 ; RUN: --args -Om1 --reg-use=s20 | FileCheck %s --check-prefix=DIS
15 ; RUN: --reg-use=s20 \
20 ; RUN: --args -Om1 --reg-use=s20 | FileCheck %s --check-prefix=DIS
33 ; ASM: vcvt.f32.s32 s20, s20
Dvsqrt.ll7 ; RUN: -reg-use s20,d20 | FileCheck %s --check-prefix=ASM
11 ; RUN: --args -Om1 -allow-extern -reg-use s20,d20 \
16 ; RUN: -reg-use s20,d20 | FileCheck %s --check-prefix=IASM
20 ; RUN: --args -Om1 -allow-extern -reg-use s20,d20 \
33 ; ASM: vsqrt.f32 s20, s20
Dvadd.ll10 ; RUN: -reg-use s20,s22,d20,d22 \
16 ; RUN: -reg-use s20,s22,d20,d22 \
21 ; RUN: -reg-use s20,s22,d20,d22 \
27 ; RUN: -reg-use s20,s22,d20,d22 \
38 ; ASM: vadd.f32 s20, s20, s22
Dvcvt.u32.f64.ll7 ; RUN: --reg-use=s20 | FileCheck %s --check-prefix=ASM
11 ; RUN: --args -Om1 --reg-use=s20 | FileCheck %s --check-prefix=DIS
15 ; RUN: --reg-use=s20 \
20 ; RUN: --args -Om1 --reg-use=s20 | FileCheck %s --check-prefix=DIS
31 ; ASM: vcvt.u32.f64 s20, d0
Dvcvt.s32.f64.ll7 ; RUN: --reg-use=s20 | FileCheck %s --check-prefix=ASM
11 ; RUN: --args -Om1 --reg-use=s20 | FileCheck %s --check-prefix=DIS
15 ; RUN: --reg-use=s20 \
20 ; RUN: --args -Om1 --reg-use=s20 | FileCheck %s --check-prefix=DIS
33 ; ASM: vcvt.s32.f64 s20, d0
Dvcvt.f64.u32.ll7 ; RUN: --reg-use=s20 | FileCheck %s --check-prefix=ASM
11 ; RUN: --args -Om1 --reg-use=s20 | FileCheck %s --check-prefix=DIS
15 ; RUN: --reg-use=s20 \
20 ; RUN: --args -Om1 --reg-use=s20 | FileCheck %s --check-prefix=DIS
33 ; ASM: vcvt.f64.u32 d0, s20
Dvcvt.f64.s32.ll7 ; RUN: --reg-use=s20 | FileCheck %s --check-prefix=ASM
11 ; RUN: --args -Om1 --reg-use=s20 | FileCheck %s --check-prefix=DIS
15 ; RUN: --reg-use=s20 \
20 ; RUN: --args -Om1 --reg-use=s20 | FileCheck %s --check-prefix=DIS
33 ; ASM: vcvt.f64.s32 d0, s20
Dvmov-imm.ll6 ; RUN: %p2i --filetype=asm -i %s --target=arm32 --args -Om1 -reg-use=d21,s20 \
11 ; RUN: --args -Om1 -reg-use=d21,s20 \
15 ; RUN: %p2i --filetype=iasm -i %s --target=arm32 --args -Om1 -reg-use=d21,s20 \
20 ; RUN: --args -Om1 -reg-use=d21,s20 \
45 ; ASM: vmov.f32 s20, #1.500000e+00
Dvmov-cast.ll9 ; RUN: -reg-use s20,s22,d20,d22 \
15 ; RUN: -reg-use s20,s22,d20,d22 \
20 ; RUN: -reg-use s20,s22,d20,d22 \
26 ; RUN: -reg-use s20,s22,d20,d22 \
40 ; ASM: vmov s20, r0
Dvabs.ll7 ; RUN: -reg-use s20,d22 \
13 ; RUN: -reg-use s20,d22 \
18 ; RUN: -reg-use s20,d22 \
24 ; RUN: -reg-use s20,d22 \
39 ; ASM: vabs.f32 s20, s20
Dpopmult.ll12 ; RUN: -reg-use s20,s22,s23 \
18 ; RUN: -reg-use s20,s22,s23 \
23 ; RUN: -reg-use s20,s22,s23 \
29 ; RUN: -reg-use s20,s22,s23 \
39 ; ASM: vpush {s20}
60 ; ASM-NEXT: vpop {s20}
Dvldr.ll7 ; RUN: -reg-use r5,s20,d20 \
13 ; RUN: -reg-use r5,s20,d20 \
18 ; RUN: -reg-use r5,s20,d20 \
24 ; RUN: -reg-use r5,s20,d20 \
37 ; ASM: vldr s20, [r5]
Dvstr.ll7 ; RUN: -reg-use r5,r6,s20,d20 \
13 ; RUN: -reg-use r5,r6,s20,d20 \
18 ; RUN: -reg-use r5,r6,s20,d20 \
24 ; RUN: -reg-use r5,r6,s20,d20 \
38 ; ASM: vstr s20, [r5]
Dvmov-fp.ll11 ; RUN: -reg-use s20,s22,d20,d22 \
17 ; RUN: -reg-use s20,s22,d20,d22 \
22 ; RUN: -reg-use s20,s22,d20,d22 \
28 ; RUN: -reg-use s20,s22,d20,d22 \
38 ; ASM: vmovne.f32 s20, s22
/external/swiftshader/third_party/llvm-7.0/llvm/test/MC/AArch64/
Dneon-scalar-saturating-add-sub.s8 sqadd s20, s21, s2
21 uqadd s20, s21, s2
34 sqsub s20, s21, s2
47 uqsub s20, s21, s2
Dneon-scalar-mul.s10 sqdmulh s20, s21, s2
20 sqrdmulh s20, s21, s2
30 fmulx s20, s22, s15
/external/capstone/suite/MC/AArch64/
Dneon-scalar-saturating-add-sub.s.cs4 0xb4,0x0e,0xa2,0x5e = sqadd s20, s21, s2
8 0xb4,0x0e,0xa2,0x7e = uqadd s20, s21, s2
12 0xb4,0x2e,0xa2,0x5e = sqsub s20, s21, s2
16 0xb4,0x2e,0xa2,0x7e = uqsub s20, s21, s2
Dneon-scalar-mul.s.cs3 0xb4,0xb6,0xa2,0x5e = sqdmulh s20, s21, s2
5 0xb4,0xb6,0xa2,0x7e = sqrdmulh s20, s21, s2
6 0xd4,0xde,0x2f,0x5e = fmulx s20, s22, s15
/external/llvm/test/MC/AArch64/
Dneon-scalar-saturating-add-sub.s8 sqadd s20, s21, s2
21 uqadd s20, s21, s2
34 sqsub s20, s21, s2
47 uqsub s20, s21, s2
Dneon-scalar-mul.s10 sqdmulh s20, s21, s2
20 sqrdmulh s20, s21, s2
30 fmulx s20, s22, s15
/external/tensorflow/tensorflow/core/platform/
Dctstring_test.cc72 TF_TString s20, s21, s22; in TEST() local
73 TF_TString_Init(&s20); in TEST()
77 TF_TString_Copy(&s20, "a", 1); in TEST()
79 EXPECT_EQ(1, TF_TString_GetSize(&s20)); in TEST()
80 EXPECT_EQ(TF_TSTR_SMALL, TF_TString_GetType(&s20)); in TEST()
81 EXPECT_STREQ("a", TF_TString_GetDataPointer(&s20)); in TEST()
82 EXPECT_STREQ("a", TF_TString_GetMutableDataPointer(&s20)); in TEST()
83 EXPECT_EQ(TF_TString_SmallCapacity, TF_TString_GetCapacity(&s20)); in TEST()
85 TF_TString_Assign(&s21, &s20); in TEST()
101 TF_TString_Dealloc(&s20); in TEST()

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