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Searched refs:sdr_pll (Results 1 – 2 of 2) sorted by relevance

/external/u-boot/arch/arm/mach-socfpga/
Dclock_manager_gen5.c95 writel(0, &clock_manager_base->sdr_pll.en); in cm_basic_init()
113 &clock_manager_base->sdr_pll.vco); in cm_basic_init()
130 readl(&clock_manager_base->sdr_pll.vco); in cm_basic_init()
139 writel(cfg->sdram_vco_base, &clock_manager_base->sdr_pll.vco); in cm_basic_init()
202 &clock_manager_base->sdr_pll.vco); in cm_basic_init()
220 &clock_manager_base->sdr_pll.ddrdqsclk); in cm_basic_init()
223 &clock_manager_base->sdr_pll.ddr2xdqsclk); in cm_basic_init()
226 &clock_manager_base->sdr_pll.ddrdqclk); in cm_basic_init()
229 &clock_manager_base->sdr_pll.s2fuser2clk); in cm_basic_init()
250 &clock_manager_base->sdr_pll.vco); in cm_basic_init()
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/external/u-boot/arch/arm/mach-socfpga/include/mach/
Dclock_manager_gen5.h109 struct socfpga_clock_manager_sdr_pll sdr_pll; member