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/external/llvm/test/Transforms/InstSimplify/
Dshr-nop.ll20 %shr = lshr exact i8 0, %a
21 %cmp = icmp eq i8 %shr, 0
29 %shr = ashr exact i8 0, %a
30 %cmp = icmp eq i8 %shr, 0
38 %shr = ashr i8 0, %a
39 %cmp = icmp eq i8 %shr, 0
47 %shr = lshr exact i8 0, %a
48 %cmp = icmp ne i8 %shr, 0
56 %shr = ashr exact i8 0, %a
57 %cmp = icmp ne i8 %shr, 0
[all …]
/external/swiftshader/third_party/llvm-7.0/llvm/test/Transforms/InstSimplify/
Dshr-nop.ll20 %shr = lshr exact i8 0, %a
21 %cmp = icmp eq i8 %shr, 0
29 %shr = ashr exact i8 0, %a
30 %cmp = icmp eq i8 %shr, 0
38 %shr = ashr i8 0, %a
39 %cmp = icmp eq i8 %shr, 0
47 %shr = lshr exact i8 0, %a
48 %cmp = icmp ne i8 %shr, 0
56 %shr = ashr exact i8 0, %a
57 %cmp = icmp ne i8 %shr, 0
[all …]
/external/llvm/test/Transforms/InstCombine/
Dicmp-shr.ll8 %shr = lshr i8 127, %a
9 %cmp = icmp eq i8 %shr, 0
16 %shr = ashr i8 127, %a
17 %cmp = icmp eq i8 %shr, 0
24 %shr = lshr i8 127, %a
25 %cmp = icmp ne i8 %shr, 0
32 %shr = ashr i8 127, %a
33 %cmp = icmp ne i8 %shr, 0
40 %shr = ashr i8 128, %a
41 %cmp = icmp eq i8 %shr, 128
[all …]
/external/swiftshader/third_party/llvm-7.0/llvm/test/Transforms/InstCombine/
Dicmp-shr.ll11 %shr = lshr i8 127, %a
12 %cmp = icmp eq i8 %shr, 0
21 %shr = lshr <2 x i8> <i8 127, i8 127>, %a
22 %cmp = icmp eq <2 x i8> %shr, zeroinitializer
31 %shr = ashr i8 127, %a
32 %cmp = icmp eq i8 %shr, 0
41 %shr = lshr i8 127, %a
42 %cmp = icmp ne i8 %shr, 0
51 %shr = ashr i8 127, %a
52 %cmp = icmp ne i8 %shr, 0
[all …]
/external/llvm/test/CodeGen/X86/
Ddagcombine-shifts.ll14 %shr = lshr i8 %v, 4
15 %ext = zext i8 %shr to i16
22 ; CHECK-NOT: shr
28 %shr = lshr i8 %v, 4
29 %ext = zext i8 %shr to i32
36 ; CHECK-NOT: shr
42 %shr = lshr i16 %v, 4
43 %ext = zext i16 %shr to i32
50 ; CHECK-NOT: shr
56 %shr = lshr i8 %v, 4
[all …]
Dshift-combine.ll25 %shr = ashr exact i32 %sub, 3
26 %gep = getelementptr inbounds i32, i32* %x, i32 %shr
35 %shr = ashr exact i32 %sub, 3
36 %gep = getelementptr inbounds i32, i32* %x, i32 %shr
45 %shr = ashr exact i32 %sub, 2
46 %gep = getelementptr inbounds i32, i32* %x, i32 %shr
55 %shr = lshr exact i32 %sub, 3
56 %gep = getelementptr inbounds i32, i32* %x, i32 %shr
65 %shr = lshr exact i32 %sub, 3
66 %gep = getelementptr inbounds i32, i32* %x, i32 %shr
[all …]
Drotate4.ll15 %shr = lshr i32 %a, %and3
16 %or = or i32 %shl, %shr
29 %shr = shl i32 %a, %and3
30 %or = or i32 %shl, %shr
43 %shr = lshr i64 %a, %and3
44 %or = or i64 %shl, %shr
57 %shr = shl i64 %a, %and3
58 %or = or i64 %shl, %shr
76 %shr = lshr i32 %a, %and3
77 %or = or i32 %shl, %shr
[all …]
/external/swiftshader/third_party/llvm-7.0/llvm/test/CodeGen/X86/
Ddagcombine-shifts.ll14 %shr = lshr i8 %v, 4
15 %ext = zext i8 %shr to i16
22 ; CHECK-NOT: shr
28 %shr = lshr i8 %v, 4
29 %ext = zext i8 %shr to i32
36 ; CHECK-NOT: shr
42 %shr = lshr i16 %v, 4
43 %ext = zext i16 %shr to i32
50 ; CHECK-NOT: shr
56 %shr = lshr i8 %v, 4
[all …]
/external/swiftshader/third_party/llvm-7.0/llvm/test/CodeGen/Mips/
Dmips64shift.ll13 %shr = ashr i64 %a0, %a1
14 ret i64 %shr
20 %shr = lshr i64 %a0, %a1
21 ret i64 %shr
34 %shr = ashr i64 %a0, 10
35 ret i64 %shr
41 %shr = lshr i64 %a0, 10
42 ret i64 %shr
55 %shr = ashr i64 %a0, 40
56 ret i64 %shr
[all …]
/external/llvm/test/CodeGen/Mips/
Dmips64shift.ll14 %shr = ashr i64 %a0, %a1
15 ret i64 %shr
21 %shr = lshr i64 %a0, %a1
22 ret i64 %shr
35 %shr = ashr i64 %a0, 10
36 ret i64 %shr
42 %shr = lshr i64 %a0, 10
43 ret i64 %shr
56 %shr = ashr i64 %a0, 40
57 ret i64 %shr
[all …]
/external/mesa3d/src/intel/tools/tests/gen7.5/
Dshr.asm1 shr(1) g11<1>UD g11<0,1,0>UD 0x00000010UD { align1 1N };
2 shr(8) g20<1>UD g19<8,8,1>UD 0x00000001UD { align1 1Q };
3 shr(16) g88<1>UD g86<8,8,1>UD 0x00000001UD { align1 1H };
4 shr(8) g10<1>.xyzUD g1<0>.xyzzUD g1.4<0>.xyzzUD { align16 1Q };
5 shr(8) g3<1>UD g2<0,1,0>UD g2.2<0,1,0>UD { align1 1Q };
6 shr(16) g3<1>UD g2<0,1,0>UD g2.2<0,1,0>UD { align1 1H };
7 shr(8) g4<1>.yUD g1<0>.xUD 0x00000010UD { align16 NoDDChk 1Q };
8 shr(1) g29<1>UD g29<0,1,0>UD 5D { align1 WE_all 1N };
9 shr(8) g8<1>.xUD g7<4>.xUD 0x00000001UD { align16 1Q };
10 shr(8) g19<2>UW g5<8,8,1>UD g4<8,8,1>UW { align1 1Q };
[all …]
/external/swiftshader/third_party/llvm-7.0/llvm/test/CodeGen/Thumb/
Dshift-and.ll12 %shr = and i32 %0, 1023
13 ret i32 %shr
29 %shr = and i32 %0, 1022
30 ret i32 %shr
41 %shr = and i32 %0, 255
42 ret i32 %shr
54 %shr = and i32 %0, -128
55 ret i32 %shr
66 %shr = and i32 %0, 536870912
67 ret i32 %shr
[all …]
/external/mesa3d/src/intel/tools/tests/gen6/
Dshr.asm1 shr(8) m18<1>D g25<4>.xUD 4D { align16 1Q };
2 shr(8) g13<1>UD g12<8,8,1>UD 0x00000001UD { align1 1Q };
3 shr(16) g19<1>UD g17<8,8,1>UD 0x00000001UD { align1 1H };
4 shr(1) g22<1>UD g22<0,1,0>UD 5D { align1 WE_all 1N };
5 shr(8) g34<1>UD g3<0>UD g1<0>.yUD { align16 1Q };
6 shr(8) g3<1>.xUD g3<4>.xUD 0x00000001UD { align16 1Q };
7 shr(8) g28<1>UD g3.5<0,1,0>UD g4.1<0,1,0>UD { align1 1Q };
8 shr(16) g48<1>UD g3.5<0,1,0>UD g4.1<0,1,0>UD { align1 1H };
9 shr(1) g3<1>D sr0<0,1,0>D 12D { align1 1N };
/external/mesa3d/src/intel/tools/tests/gen8/
Dshr.asm1 shr(8) g20<1>UD g19<8,8,1>UD 0x00000001UD { align1 1Q };
2 shr(16) g51<1>UD g49<8,8,1>UD 0x00000001UD { align1 1H };
3 shr(16) g4<1>UW g1<1,8,0>UB 0x44440000V { align1 1H };
4 shr.z.f0.0(8) g3<1>UD g1<8,8,1>UD 0x0000001bUD { align1 1Q };
5 shr.z.f0.0(8) null<1>UD g1<8,8,1>UD 0x0000001bUD { align1 1Q };
6 shr(8) g3<1>UW g1.28<1,8,0>UB 0x76543210V { align1 1Q };
7 shr(8) g3<2>UW g5<8,8,1>UD g4<8,8,1>UW { align1 1Q };
8 shr(16) g20<2>UW g15<8,8,1>UD g13<8,8,1>UW { align1 1H };
/external/mesa3d/src/intel/tools/tests/gen7/
Dshr.asm1 shr(1) g11<1>UD g11<0,1,0>UD 0x0000000fUD { align1 1N };
2 shr(8) g13<1>.xUD g5.4<0>.zUD g5.4<0>.wUD { align16 1Q };
3 shr(8) g13<1>UD g12<8,8,1>UD 0x00000001UD { align1 1Q };
4 shr(16) g27<1>UD g25<8,8,1>UD 0x00000001UD { align1 1H };
5 shr(8) g35<1>UD g31<8,8,1>UD g5.5<0,1,0>UD { align1 1Q };
6 shr(16) g23<1>UD g56<8,8,1>UD g7.5<0,1,0>UD { align1 1H };
7 shr(1) g9<1>UD g9<0,1,0>UD 5D { align1 WE_all 1N };
8 shr(8) g54<1>.xUD g55<4>.xUD 0x00000005UD { align16 1Q };
/external/mesa3d/src/intel/tools/tests/gen9/
Dshr.asm1 shr(8) g20<1>UD g19<8,8,1>UD 0x00000001UD { align1 1Q };
2 shr(16) g43<1>UD g41<8,8,1>UD 0x00000001UD { align1 1H };
3 shr.z.f0.0(8) g3<1>UD g1<8,8,1>UD 0x0000001bUD { align1 1Q };
4 shr(16) g8<1>UW g1<1,8,0>UB 0x44440000V { align1 1H };
5 shr.z.f0.0(8) null<1>UD g1<8,8,1>UD 0x0000001bUD { align1 1Q };
6 shr(8) g3<1>UW g1.28<1,8,0>UB 0x76543210V { align1 1Q };
7 shr(8) g3<2>UW g5<8,8,1>UD g4<8,8,1>UW { align1 1Q };
8 shr(16) g20<2>UW g15<8,8,1>UD g13<8,8,1>UW { align1 1H };
/external/swiftshader/third_party/llvm-7.0/llvm/test/Transforms/IndVarSimplify/
Div-fold.ll5 ; Indvars should be able to fold IV increments into shr when low bits are zero.
8 ; CHECK: shr.1 = lshr i32 %0, 5
15 %shr = lshr i32 %0, 5
16 %arrayidx = getelementptr inbounds i32, i32* %bitmap, i32 %shr
19 %shr.1 = lshr i32 %inc.1, 5
20 %arrayidx.1 = getelementptr inbounds i32, i32* %bitmap, i32 %shr.1
31 ; Invdars should not fold an increment into shr unless 2^shiftBits is
35 ; CHECK: shr.1 = lshr i32 %inc.1, 5
42 %shr = lshr i32 %0, 5
43 %arrayidx = getelementptr inbounds i32, i32* %bitmap, i32 %shr
[all …]
/external/llvm/test/Transforms/IndVarSimplify/
Div-fold.ll5 ; Indvars should be able to fold IV increments into shr when low bits are zero.
8 ; CHECK: shr.1 = lshr i32 %0, 5
15 %shr = lshr i32 %0, 5
16 %arrayidx = getelementptr inbounds i32, i32* %bitmap, i32 %shr
19 %shr.1 = lshr i32 %inc.1, 5
20 %arrayidx.1 = getelementptr inbounds i32, i32* %bitmap, i32 %shr.1
31 ; Invdars should not fold an increment into shr unless 2^shiftBits is
35 ; CHECK: shr.1 = lshr i32 %inc.1, 5
42 %shr = lshr i32 %0, 5
43 %arrayidx = getelementptr inbounds i32, i32* %bitmap, i32 %shr
[all …]
/external/swiftshader/third_party/llvm-7.0/llvm/test/CodeGen/BPF/
Dshifts.ll7 %shr = lshr i8 %a, %cnt
8 ret i8 %shr
15 %shr = ashr i8 %a, %cnt
16 ret i8 %shr
31 %shr = lshr i16 %a, %cnt
32 ret i16 %shr
39 %shr = ashr i16 %a, %cnt
40 ret i16 %shr
56 %shr = lshr i32 %a, %cnt
57 ret i32 %shr
[all …]
/external/llvm/test/CodeGen/BPF/
Dshifts.ll7 %shr = lshr i8 %a, %cnt
8 ret i8 %shr
15 %shr = ashr i8 %a, %cnt
16 ret i8 %shr
31 %shr = lshr i16 %a, %cnt
32 ret i16 %shr
39 %shr = ashr i16 %a, %cnt
40 ret i16 %shr
56 %shr = lshr i32 %a, %cnt
57 ret i32 %shr
[all …]
/external/llvm/test/MC/Mips/
Dmips64shift.ll17 %shr = ashr i64 %a0, 10
18 ret i64 %shr
24 %shr = lshr i64 %a0, 10
25 ret i64 %shr
38 %shr = ashr i64 %a0, 40
39 ret i64 %shr
45 %shr = lshr i64 %a0, 40
46 ret i64 %shr
/external/swiftshader/third_party/llvm-7.0/llvm/test/MC/Mips/
Dmips64shift.ll17 %shr = ashr i64 %a0, 10
18 ret i64 %shr
24 %shr = lshr i64 %a0, 10
25 ret i64 %shr
38 %shr = ashr i64 %a0, 40
39 ret i64 %shr
45 %shr = lshr i64 %a0, 40
46 ret i64 %shr
/external/llvm/test/CodeGen/SystemZ/
Dshift-10.ll11 %shr = lshr i32 %a, 1
12 %trunc = trunc i32 %shr to i1
24 %shr = lshr i32 %a, 30
25 %trunc = trunc i32 %shr to i1
36 %shr = lshr i32 %a, 1
37 %ext = zext i32 %shr to i64
48 %shr = lshr i32 %a, 30
49 %ext = sext i32 %shr to i64
62 %shr = lshr i32 %a, 30
63 %ext = sext i32 %shr to i64
[all …]
/external/swiftshader/third_party/llvm-7.0/llvm/test/CodeGen/SystemZ/
Dshift-10.ll11 %shr = lshr i32 %a, 1
12 %trunc = trunc i32 %shr to i1
24 %shr = lshr i32 %a, 30
25 %trunc = trunc i32 %shr to i1
36 %shr = lshr i32 %a, 1
37 %ext = zext i32 %shr to i64
48 %shr = lshr i32 %a, 30
49 %ext = sext i32 %shr to i64
62 %shr = lshr i32 %a, 30
63 %ext = sext i32 %shr to i64
[all …]
/external/llvm/test/CodeGen/MSP430/
Dshifts.ll9 %shr = lshr i8 %a, %cnt
10 ret i8 %shr
17 %shr = ashr i8 %a, %cnt
18 ret i8 %shr
33 %shr = lshr i16 %a, %cnt
34 ret i16 %shr
41 %shr = ashr i16 %a, %cnt
42 ret i16 %shr

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