/external/mesa3d/src/gallium/drivers/radeonsi/ |
D | si_pipe.h | 259 struct si_resource { struct 309 struct si_resource *staging; argument 314 struct si_resource buffer; 329 struct si_resource *cmask_buffer; 377 struct si_resource *dcc_separate_buffer; 379 struct si_resource *last_dcc_separate_buffer; 389 struct si_resource *dcc_retile_buffer; 753 struct si_resource *buf_filled_size; 875 struct si_resource *trace_buf; 885 struct si_resource *dst; [all …]
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D | si_buffer.c | 46 void *si_buffer_map_sync_with_rings(struct si_context *sctx, struct si_resource *resource, in si_buffer_map_sync_with_rings() 100 void si_init_resource_fields(struct si_screen *sscreen, struct si_resource *res, uint64_t size, in si_init_resource_fields() 214 bool si_alloc_resource(struct si_screen *sscreen, struct si_resource *res) in si_alloc_resource() 262 struct si_resource *buffer = si_resource(buf); in si_buffer_destroy() 276 static bool si_invalidate_buffer(struct si_context *sctx, struct si_resource *buf) in si_invalidate_buffer() 310 struct si_resource *sdst = si_resource(dst); in si_replace_buffer_storage() 311 struct si_resource *ssrc = si_resource(src); in si_replace_buffer_storage() 332 struct si_resource *buf = si_resource(resource); in si_invalidate_resource() 342 struct si_resource *staging, unsigned offset) in si_buffer_get_transfer() 373 struct si_resource *buf = si_resource(resource); in si_buffer_transfer_map() [all …]
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D | si_cp_dma.c | 171 radeon_add_to_buffer_list(sctx, sctx->gfx_cs, si_resource(dst), RADEON_USAGE_WRITE, in si_cp_dma_prepare() 174 radeon_add_to_buffer_list(sctx, sctx->gfx_cs, si_resource(src), RADEON_USAGE_READ, in si_cp_dma_prepare() 205 struct si_resource *sdst = si_resource(dst); in si_cp_dma_clear_buffer() 309 util_range_add(dst, &si_resource(dst)->valid_buffer_range, dst_offset, dst_offset + size); in si_cp_dma_copy_buffer() 312 dst_offset += si_resource(dst)->gpu_address; in si_cp_dma_copy_buffer() 315 src_offset += si_resource(src)->gpu_address; in si_cp_dma_copy_buffer() 343 bool secure = src && (si_resource(src)->flags & RADEON_FLAG_ENCRYPTED); in si_cp_dma_copy_buffer() 344 assert(!secure || (!dst || (si_resource(dst)->flags & RADEON_FLAG_ENCRYPTED))); in si_cp_dma_copy_buffer() 393 si_resource(dst)->TC_L2_dirty = true; in si_cp_dma_copy_buffer() 574 void si_cp_write_data(struct si_context *sctx, struct si_resource *buf, unsigned offset, in si_cp_write_data() [all …]
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D | si_dma_cs.c | 39 void si_dma_emit_timestamp(struct si_context *sctx, struct si_resource *dst, uint64_t offset) in si_dma_emit_timestamp() 70 struct si_resource *sdst = si_resource(dst); in si_sdma_clear_buffer() 134 struct si_resource *sdst = si_resource(dst); in si_sdma_copy_buffer() 135 struct si_resource *ssrc = si_resource(src); in si_sdma_copy_buffer() 213 void si_need_dma_space(struct si_context *ctx, unsigned num_dw, struct si_resource *dst, in si_need_dma_space() 214 struct si_resource *src) in si_need_dma_space()
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D | si_query.h | 39 struct si_resource; 174 void (*emit_start)(struct si_context *, struct si_query_hw *, struct si_resource *buffer, 176 void (*emit_stop)(struct si_context *, struct si_query_hw *, struct si_resource *buffer, 185 struct si_resource *buf; 215 struct si_resource *workaround_buf;
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D | si_descriptors.c | 194 static inline enum radeon_bo_priority si_get_sampler_view_priority(struct si_resource *res) in si_get_sampler_view_priority() 272 struct si_resource *res = si_resource(sview->base.texture); in si_sampler_views_check_encrypted() 280 static void si_set_buf_desc_address(struct si_resource *buf, uint64_t offset, uint32_t *state) in si_set_buf_desc_address() 680 struct si_resource *res = si_resource(view->resource); in si_mark_image_range_valid() 693 struct si_resource *res; in si_set_shader_image_desc() 695 res = si_resource(view->resource); in si_set_shader_image_desc() 762 struct si_resource *res; in si_set_shader_image() 769 res = si_resource(view->resource); in si_set_shader_image() 1006 sctx, sctx->gfx_cs, si_resource(buffers->buffers[i]), in si_buffer_resources_begin_new_cs() 1022 (si_resource(buffers->buffers[i])->flags & RADEON_FLAG_ENCRYPTED)) in si_buffer_resources_check_encrypted() [all …]
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D | si_state_draw.c | 219 si_resource(sctx->tess_rings_tmz) : si_resource(sctx->tess_rings))->gpu_address; in si_emit_derived_tess_state() 829 index_va = si_resource(indexbuf)->gpu_address + index_offset; in si_emit_draw_packets() 831 radeon_add_to_buffer_list(sctx, sctx->gfx_cs, si_resource(indexbuf), RADEON_USAGE_READ, in si_emit_draw_packets() 844 uint64_t indirect_va = si_resource(indirect->buffer)->gpu_address; in si_emit_draw_packets() 855 radeon_add_to_buffer_list(sctx, sctx->gfx_cs, si_resource(indirect->buffer), in si_emit_draw_packets() 882 struct si_resource *params_buf = si_resource(indirect->indirect_draw_count); in si_emit_draw_packets() 1148 struct si_resource* wait_mem_scratch = unlikely(ctx->ws->cs_is_secure(cs)) ? in gfx10_emit_cache_flush() 1378 struct si_resource* wait_mem_scratch = unlikely(sctx->ws->cs_is_secure(cs)) ? in si_emit_cache_flush() 1500 struct si_resource *buf; in si_upload_vertex_buffer_descriptors() 1506 buf = si_resource(vb->buffer.resource); in si_upload_vertex_buffer_descriptors() [all …]
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D | si_compute.c | 340 va = si_resource(resources[i])->gpu_address; in si_set_global_binding() 595 struct si_resource *dispatch_buf = NULL; in si_setup_user_sgprs_co_v2() 655 struct si_resource *input_buffer = NULL; in si_upload_compute_input() 700 COPY_DATA_SRC_MEM, si_resource(info->indirect), in si_setup_nir_user_data() 776 uint64_t base_va = si_resource(info->indirect)->gpu_address; in si_emit_dispatch_packets() 778 radeon_add_to_buffer_list(sctx, sctx->gfx_cs, si_resource(info->indirect), RADEON_USAGE_READ, in si_emit_dispatch_packets() 837 if (sctx->chip_class <= GFX8 && si_resource(info->indirect)->TC_L2_dirty) { in si_launch_grid() 839 si_resource(info->indirect)->TC_L2_dirty = false; in si_launch_grid() 879 struct si_resource *buffer = si_resource(program->global_buffers[i]); in si_launch_grid()
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D | si_compute_blit.c | 271 si_resource(dst)->TC_L2_dirty = true; in si_compute_do_clear_or_copy() 339 si_resource(dst)->domains & RADEON_DOMAIN_VRAM) { in si_clear_buffer() 346 si_resource(dst)->domains & RADEON_DOMAIN_GTT) { in si_clear_buffer() 397 si_resource(dst)->domains & RADEON_DOMAIN_VRAM && in si_copy_buffer() 398 si_resource(src)->domains & RADEON_DOMAIN_VRAM) { in si_copy_buffer() 406 (si_resource(dst)->domains | si_resource(src)->domains) & RADEON_DOMAIN_GTT) { in si_copy_buffer() 413 if (sctx->screen->info.has_dedicated_vram && si_resource(dst)->domains & RADEON_DOMAIN_VRAM && in si_copy_buffer() 414 si_resource(src)->domains & RADEON_DOMAIN_VRAM && size > compute_min_size && in si_copy_buffer()
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D | si_state.h | 143 struct si_resource *instance_divisor_factor_buffer; 432 struct si_resource *buffer; 509 void si_upload_const_buffer(struct si_context *sctx, struct si_resource **buf, const uint8_t *ptr, 532 void si_make_buffer_descriptor(struct si_screen *screen, struct si_resource *buf,
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D | si_state_streamout.c | 44 struct si_resource *buf = si_resource(buffer); in si_create_so_target() 108 si_resource(sctx->streamout.targets[i]->b.buffer)->TC_L2_dirty = true; in si_set_streamout_targets() 201 si_resource(targets[i]->buffer)->bind_history |= PIPE_BIND_STREAM_OUTPUT; in si_set_streamout_targets()
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D | si_fence.c | 35 struct si_resource *buf; 70 struct si_resource *buf, uint64_t va, uint32_t new_fence, in si_cp_release_mem() 90 struct si_resource *scratch = unlikely(ctx->ws->cs_is_secure(ctx->gfx_cs)) ? in si_cp_release_mem() 114 struct si_resource *scratch = ctx->eop_bug_scratch; in si_cp_release_mem()
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D | si_gfx_cs.c | 280 si_resource(pipe_buffer_create(ctx->b.screen, 0, PIPE_USAGE_STAGING, 8)); in si_begin_gfx_cs_debug() 453 … unlikely(is_secure) ? si_resource(ctx->tess_rings_tmz) : si_resource(ctx->tess_rings), in si_begin_new_gfx_cs()
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D | si_shader.h | 727 struct si_resource *bo; 728 struct si_resource *scratch_bo;
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D | gfx10_query.c | 43 struct si_resource *buf; 146 qbuf->buf = si_resource(pipe_buffer_create(&screen->b, 0, PIPE_USAGE_STAGING, buf_size)); in gfx10_alloc_query_buffer()
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D | si_query.c | 639 buffer->buf = si_resource(pipe_buffer_create(&screen->b, 0, PIPE_USAGE_STAGING, buf_size)); in si_query_buffer_alloc() 708 struct si_resource *buffer, uint64_t va); 710 struct si_resource *buffer, uint64_t va); 833 struct si_resource *buffer, uint64_t va) in si_query_hw_do_emit_start() 897 struct si_resource *buffer, uint64_t va) in si_query_hw_do_emit_stop() 991 static void emit_set_predicate(struct si_context *ctx, struct si_resource *buf, uint64_t va, in emit_set_predicate() 1555 si_resource(resource)->TC_L2_dirty = true; in si_query_hw_get_result_resource()
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D | si_cp_reg_shadowing.c | 32 struct si_resource *shadow_regs) in si_build_load_reg()
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D | si_texture.c | 676 struct si_resource *res = si_resource(resource); in si_texture_get_handle() 689 res = si_resource(resource); in si_texture_get_handle() 811 struct si_resource *resource = &tex->buffer; in si_texture_destroy() 986 struct si_resource *resource; in si_texture_create_object() 1177 struct si_resource *buf = si_aligned_buffer_create(screen, in si_texture_create_object() 1636 struct si_resource *buf; in si_texture_transfer_map() 1779 struct si_resource *buf = stransfer->staging ? stransfer->staging : &tex->buffer; in si_texture_transfer_unmap()
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D | si_perfcounter.c | 831 static void si_pc_emit_start(struct si_context *sctx, struct si_resource *buffer, uint64_t va) in si_pc_emit_start() 848 static void si_pc_emit_stop(struct si_context *sctx, struct si_resource *buffer, uint64_t va) in si_pc_emit_stop()
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D | si_pipe.c | 540 sctx->border_color_buffer = si_resource(pipe_buffer_create( in si_create_context() 876 si_resource(buf)->gpu_address = 0; /* cause a VM fault */ in si_test_vmfault()
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D | si_state.c | 3535 void si_make_buffer_descriptor(struct si_screen *screen, struct si_resource *buf, in si_make_buffer_descriptor() 4181 si_make_buffer_descriptor(sctx->screen, si_resource(texture), state->format, in si_create_sampler_view_custom() 4723 v->instance_divisor_factor_buffer = (struct si_resource *)pipe_buffer_create( in si_create_vertex_elements() 4821 si_resource(buf)->bind_history |= PIPE_BIND_VERTEX_BUFFER; in si_set_vertex_buffers() 4862 si_upload_const_buffer(sctx, (struct si_resource **)&cb.buffer, (void *)array, sizeof(array), in si_set_tess_state()
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D | si_debug.c | 646 struct si_resource *buf;
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/external/mesa3d/src/gallium/drivers/radeon/ |
D | radeon_video.c | 65 buffer->res = si_resource(pipe_buffer_create(screen, PIPE_BIND_SHARED, usage, size)); in si_vid_create_buffer() 76 buffer->res = si_resource(pipe_buffer_create(screen, PIPE_BIND_SHARED | PIPE_BIND_PROTECTED, in si_vid_create_tmz_buffer()
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D | radeon_video.h | 42 struct si_resource *res;
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D | radeon_vcn_dec.c | 1013 decode->dt_size = si_resource(((struct vl_video_buffer *)target)->resources[0])->buf->size + in rvcn_dec_message_decode() 1014 si_resource(((struct vl_video_buffer *)target)->resources[1])->buf->size; in rvcn_dec_message_decode()
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