| /external/swiftshader/third_party/llvm-7.0/llvm/test/CodeGen/Thumb2/ |
| D | thumb2-mulhi.ll | 5 ; CHECK: smmul r0, r1, r0
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| /external/llvm/test/CodeGen/Thumb2/ |
| D | thumb2-mulhi.ll | 5 ; CHECK: smmul r0, r1, r0
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| /external/llvm/test/CodeGen/ARM/ |
| D | urem-opt-size.ll | 15 ; CHECK-NOT: smmul
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| D | mulhi.ll | 7 ; V6: smmul
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| /external/swiftshader/third_party/llvm-7.0/llvm/test/CodeGen/ARM/ |
| D | mulhi.ll | 7 ; V6: smmul
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| D | dsp-mlal.ll | 47 ; CHECK: smmul r0, {{(r0, r1|r1, r0)}}
49 ; NODSP-NOT: smmul
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| D | urem-opt-size.ll | 20 ; CHECK-NOT: smmul
|
| /external/vixl/test/aarch32/ |
| D | test-assembler-cond-rd-rn-rm-t32.cc | 66 M(smmul) \
|
| D | test-assembler-cond-rd-rn-rm-a32.cc | 67 M(smmul) \
|
| /external/v8/src/codegen/arm/ |
| D | assembler-arm.h | 514 void smmul(Register dst, Register src1, Register src2, Condition cond = al);
|
| D | assembler-arm.cc | 1712 void Assembler::smmul(Register dst, Register src1, Register src2, in smmul() function in v8::internal::Assembler
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| /external/capstone/suite/MC/ARM/ |
| D | basic-arm-instructions.s.cs | 689 0x13,0xf4,0x52,0xe7 = smmul r2, r3, r4
|
| D | basic-thumb2-instructions.s.cs | 769 0x53,0xfb,0x04,0xf2 = smmul r2, r3, r4
|
| /external/vixl/src/aarch32/ |
| D | assembler-aarch32.h | 3195 void smmul(Condition cond, Register rd, Register rn, Register rm);
3196 void smmul(Register rd, Register rn, Register rm) { smmul(al, rd, rn, rm); } in smmul() function
|
| D | disasm-aarch32.h | 1157 void smmul(Condition cond, Register rd, Register rn, Register rm);
|
| /external/llvm/test/MC/ARM/ |
| D | basic-arm-instructions.s | 2519 smmul r2, r3, r4
2524 @ CHECK: smmul r2, r3, r4 @ encoding: [0x13,0xf4,0x52,0xe7]
|
| D | basic-thumb2-instructions.s | 2435 smmul r2, r3, r4
2441 @ CHECK: smmul r2, r3, r4 @ encoding: [0x53,0xfb,0x04,0xf2]
|
| /external/swiftshader/third_party/llvm-7.0/llvm/test/MC/ARM/ |
| D | basic-thumb2-instructions.s | 2483 smmul r2, r3, r4
2489 @ CHECK: smmul r2, r3, r4 @ encoding: [0x53,0xfb,0x04,0xf2]
|
| D | basic-arm-instructions.s | 2521 smmul r2, r3, r4
2526 @ CHECK: smmul r2, r3, r4 @ encoding: [0x13,0xf4,0x52,0xe7]
|
| /external/swiftshader/third_party/llvm-7.0/llvm/test/MC/Disassembler/ARM/ |
| D | basic-arm-instructions.txt | 1727 # CHECK: smmul r2, r3, r4
|
| /external/llvm/test/MC/Disassembler/ARM/ |
| D | basic-arm-instructions.txt | 1727 # CHECK: smmul r2, r3, r4
|
| /external/v8/src/compiler/backend/arm/ |
| D | code-generator-arm.cc | 1138 __ smmul(i.OutputRegister(), i.InputRegister(0), i.InputRegister(1)); in AssembleArchInstruction() local
|
| /external/llvm/lib/Target/ARM/ |
| D | ARMInstrThumb2.td | 2608 "smmul", "\t$Rd, $Rn, $Rm",
|
| /external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/ARM/ |
| D | ARMInstrThumb2.td | 2680 def t2SMMUL : T2SMMUL<0b0000, "smmul", [(set rGPR:$Rd, (mulhs rGPR:$Rn,
|
| /external/swiftshader/third_party/llvm-7.0/configs/common/lib/Target/ARM/ |
| D | ARMGenAsmMatcher.inc | 7757 "ar\005smmls\006smmlsr\005smmul\006smmulr\005smuad\006smuadx\006smulbb\006"
8721 …{ 1143 /* smmul */, ARM::t2SMMUL, Convert__Reg1_1__Reg1_2__Reg1_3__CondCode2_0, Feature_IsThumb2|F…
8722 …{ 1143 /* smmul */, ARM::SMMUL, Convert__Reg1_1__Reg1_2__Reg1_3__CondCode2_0, Feature_IsARM|Featur…
|