Searched refs:spsr_und (Results 1 – 10 of 10) sorted by relevance
/external/arm-trusted-firmware/include/arch/aarch32/ |
D | smccc_macros.S | 79 mrs r9, spsr_und 221 msr spsr_und, r9
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D | smccc_helpers.h | 67 u_register_t spsr_und; member
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/external/llvm/test/MC/ARM/ |
D | move-banked-regs.s | 83 mrs r12, spsr_und 193 msr spsr_und, r12
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/external/swiftshader/third_party/llvm-7.0/llvm/test/MC/ARM/ |
D | move-banked-regs.s | 83 mrs r12, spsr_und 193 msr spsr_und, r12
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/external/swiftshader/third_party/llvm-7.0/configs/common/lib/Target/ARM/ |
D | ARMGenSystemRegister.inc | 35 spsr_und = 32, 118 { "spsr_und", 0x36 }, // 30
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/external/arm-trusted-firmware/lib/el3_runtime/aarch64/ |
D | context.S | 78 mrs x12, spsr_und 176 msr spsr_und, x12
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/external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/ARM/ |
D | ARMSystemRegister.td | 154 def : BankedReg<"spsr_und", 0x36>;
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/external/arm-trusted-firmware/bl31/aarch64/ |
D | crash_reporting.S | 297 mrs x11, spsr_und
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/external/capstone/suite/MC/AArch64/ |
D | basic-a64-instructions.s.cs | 1572 0x4c,0x43,0x1c,0xd5 = msr spsr_und, x12 1884 0x49,0x43,0x3c,0xd5 = mrs x9, spsr_und
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/external/arm-trusted-firmware/docs/design/ |
D | firmware-design.rst | 1226 spsr_und :0x0000000000000000
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