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/external/llvm/test/CodeGen/AArch64/
Darm64-neon-v8.1a.ll5 declare <4 x i16> @llvm.aarch64.neon.sqrdmulh.v4i16(<4 x i16>, <4 x i16>)
6 declare <8 x i16> @llvm.aarch64.neon.sqrdmulh.v8i16(<8 x i16>, <8 x i16>)
7 declare <2 x i32> @llvm.aarch64.neon.sqrdmulh.v2i32(<2 x i32>, <2 x i32>)
8 declare <4 x i32> @llvm.aarch64.neon.sqrdmulh.v4i32(<4 x i32>, <4 x i32>)
9 declare i32 @llvm.aarch64.neon.sqrdmulh.i32(i32, i32)
10 declare i16 @llvm.aarch64.neon.sqrdmulh.i16(i16, i16)
32 %prod = call <4 x i16> @llvm.aarch64.neon.sqrdmulh.v4i16(<4 x i16> %mhs, <4 x i16> %rhs)
34 ; CHECK-V8a: sqrdmulh v1.4h, v1.4h, v2.4h
42 %prod = call <8 x i16> @llvm.aarch64.neon.sqrdmulh.v8i16(<8 x i16> %mhs, <8 x i16> %rhs)
44 ; CHECK-V8a: sqrdmulh v1.8h, v1.8h, v2.8h
[all …]
Darm64-neon-mul-div.ll737 declare <4 x i16> @llvm.aarch64.neon.sqrdmulh.v4i16(<4 x i16>, <4 x i16>)
738 declare <8 x i16> @llvm.aarch64.neon.sqrdmulh.v8i16(<8 x i16>, <8 x i16>)
739 declare <2 x i32> @llvm.aarch64.neon.sqrdmulh.v2i32(<2 x i32>, <2 x i32>)
740 declare <4 x i32> @llvm.aarch64.neon.sqrdmulh.v4i32(<4 x i32>, <4 x i32>)
744 %prod = call <4 x i16> @llvm.aarch64.neon.sqrdmulh.v4i16(<4 x i16> %lhs, <4 x i16> %rhs)
745 ; CHECK: sqrdmulh v0.4h, v0.4h, v1.4h
751 %prod = call <8 x i16> @llvm.aarch64.neon.sqrdmulh.v8i16(<8 x i16> %lhs, <8 x i16> %rhs)
752 ; CHECK: sqrdmulh v0.8h, v0.8h, v1.8h
758 %prod = call <2 x i32> @llvm.aarch64.neon.sqrdmulh.v2i32(<2 x i32> %lhs, <2 x i32> %rhs)
759 ; CHECK: sqrdmulh v0.2s, v0.2s, v1.2s
[all …]
Darm64-vmul.ll174 ;CHECK: sqrdmulh.4h
177 %tmp3 = call <4 x i16> @llvm.aarch64.neon.sqrdmulh.v4i16(<4 x i16> %tmp1, <4 x i16> %tmp2)
183 ;CHECK: sqrdmulh.8h
186 %tmp3 = call <8 x i16> @llvm.aarch64.neon.sqrdmulh.v8i16(<8 x i16> %tmp1, <8 x i16> %tmp2)
192 ;CHECK: sqrdmulh.2s
195 %tmp3 = call <2 x i32> @llvm.aarch64.neon.sqrdmulh.v2i32(<2 x i32> %tmp1, <2 x i32> %tmp2)
201 ;CHECK: sqrdmulh.4s
204 %tmp3 = call <4 x i32> @llvm.aarch64.neon.sqrdmulh.v4i32(<4 x i32> %tmp1, <4 x i32> %tmp2)
210 ;CHECK: sqrdmulh s0, {{s[0-9]+}}, {{s[0-9]+}}
213 %tmp3 = call i32 @llvm.aarch64.neon.sqrdmulh.i32(i32 %tmp1, i32 %tmp2)
[all …]
/external/swiftshader/third_party/llvm-7.0/llvm/test/CodeGen/AArch64/
Darm64-neon-v8.1a.ll8 declare <4 x i16> @llvm.aarch64.neon.sqrdmulh.v4i16(<4 x i16>, <4 x i16>)
9 declare <8 x i16> @llvm.aarch64.neon.sqrdmulh.v8i16(<8 x i16>, <8 x i16>)
10 declare <2 x i32> @llvm.aarch64.neon.sqrdmulh.v2i32(<2 x i32>, <2 x i32>)
11 declare <4 x i32> @llvm.aarch64.neon.sqrdmulh.v4i32(<4 x i32>, <4 x i32>)
12 declare i32 @llvm.aarch64.neon.sqrdmulh.i32(i32, i32)
13 declare i16 @llvm.aarch64.neon.sqrdmulh.i16(i16, i16)
35 %prod = call <4 x i16> @llvm.aarch64.neon.sqrdmulh.v4i16(<4 x i16> %mhs, <4 x i16> %rhs)
37 ; CHECK-V8a: sqrdmulh v1.4h, v1.4h, v2.4h
45 %prod = call <8 x i16> @llvm.aarch64.neon.sqrdmulh.v8i16(<8 x i16> %mhs, <8 x i16> %rhs)
47 ; CHECK-V8a: sqrdmulh v1.8h, v1.8h, v2.8h
[all …]
Darm64-neon-mul-div.ll737 declare <4 x i16> @llvm.aarch64.neon.sqrdmulh.v4i16(<4 x i16>, <4 x i16>)
738 declare <8 x i16> @llvm.aarch64.neon.sqrdmulh.v8i16(<8 x i16>, <8 x i16>)
739 declare <2 x i32> @llvm.aarch64.neon.sqrdmulh.v2i32(<2 x i32>, <2 x i32>)
740 declare <4 x i32> @llvm.aarch64.neon.sqrdmulh.v4i32(<4 x i32>, <4 x i32>)
744 %prod = call <4 x i16> @llvm.aarch64.neon.sqrdmulh.v4i16(<4 x i16> %lhs, <4 x i16> %rhs)
745 ; CHECK: sqrdmulh v0.4h, v0.4h, v1.4h
751 %prod = call <8 x i16> @llvm.aarch64.neon.sqrdmulh.v8i16(<8 x i16> %lhs, <8 x i16> %rhs)
752 ; CHECK: sqrdmulh v0.8h, v0.8h, v1.8h
758 %prod = call <2 x i32> @llvm.aarch64.neon.sqrdmulh.v2i32(<2 x i32> %lhs, <2 x i32> %rhs)
759 ; CHECK: sqrdmulh v0.2s, v0.2s, v1.2s
[all …]
Darm64-vmul.ll174 ;CHECK: sqrdmulh.4h
177 %tmp3 = call <4 x i16> @llvm.aarch64.neon.sqrdmulh.v4i16(<4 x i16> %tmp1, <4 x i16> %tmp2)
183 ;CHECK: sqrdmulh.8h
186 %tmp3 = call <8 x i16> @llvm.aarch64.neon.sqrdmulh.v8i16(<8 x i16> %tmp1, <8 x i16> %tmp2)
192 ;CHECK: sqrdmulh.2s
195 %tmp3 = call <2 x i32> @llvm.aarch64.neon.sqrdmulh.v2i32(<2 x i32> %tmp1, <2 x i32> %tmp2)
201 ;CHECK: sqrdmulh.4s
204 %tmp3 = call <4 x i32> @llvm.aarch64.neon.sqrdmulh.v4i32(<4 x i32> %tmp1, <4 x i32> %tmp2)
210 ;CHECK: sqrdmulh s0, {{s[0-9]+}}, {{s[0-9]+}}
213 %tmp3 = call i32 @llvm.aarch64.neon.sqrdmulh.i32(i32 %tmp1, i32 %tmp2)
[all …]
/external/swiftshader/third_party/llvm-7.0/llvm/test/MC/AArch64/
Dneon-scalar-by-elem-saturating-mul.s43 sqrdmulh h31, h30, v14.h[2]
44 sqrdmulh h1, h1, v1.h[4]
45 sqrdmulh h21, h22, v15.h[7]
46 sqrdmulh s5, s6, v7.s[2]
47 sqrdmulh s20, s26, v27.s[1]
Darm64-v128_lo-diagnostics.s4 sqrdmulh v0.8h, v1.8h, v16.h[0]
7 sqrdmulh h0, h1, v16.h[0]
Dneon-mul-div-instructions.s68 sqrdmulh v2.4h, v25.4h, v3.4h
69 sqrdmulh v12.8h, v5.8h, v13.8h
70 sqrdmulh v3.2s, v1.2s, v30.2s
Dneon-scalar-mul.s19 sqrdmulh h10, h11, h12
20 sqrdmulh s20, s21, s2
Dneon-2velem.s275 sqrdmulh v0.4h, v1.4h, v2.h[2]
276 sqrdmulh v0.8h, v1.8h, v2.h[2]
277 sqrdmulh v0.2s, v1.2s, v2.s[2]
278 sqrdmulh v0.2s, v1.2s, v22.s[2]
279 sqrdmulh v0.4s, v1.4s, v2.s[2]
280 sqrdmulh v0.4s, v1.4s, v22.s[2]
Dneon-diagnostics.s906 sqrdmulh h10, s11, h12
907 sqrdmulh s20, h21, s2
1266 sqrdmulh v2.2s, v25.4s, v3.4s
1267 sqrdmulh v12.16b, v5.16b, v13.16b
1268 sqrdmulh v3.4h, v1.4h, v30.2d
3611 sqrdmulh v0.4h, v1.4h, v2.h[8]
3612 sqrdmulh v0.4h, v1.4h, v16.h[2]
3613 sqrdmulh v0.8h, v1.8h, v2.h[8]
3614 sqrdmulh v0.8h, v1.8h, v16.h[2]
3615 sqrdmulh v0.2s, v1.2s, v2.s[4]
[all …]
/external/capstone/suite/MC/AArch64/
Dneon-scalar-by-elem-saturating-mul.s.cs14 0xdf,0xd3,0x6e,0x5f = sqrdmulh h31, h30, v14.h[2]
15 0x21,0xd8,0x41,0x5f = sqrdmulh h1, h1, v1.h[4]
16 0xd5,0xda,0x7f,0x5f = sqrdmulh h21, h22, v15.h[7]
17 0xc5,0xd8,0x87,0x5f = sqrdmulh s5, s6, v7.s[2]
18 0x54,0xd3,0xbb,0x5f = sqrdmulh s20, s26, v27.s[1]
Dneon-mul-div-instructions.s.cs19 0x22,0xb7,0x63,0x2e = sqrdmulh v2.4h, v25.4h, v3.4h
20 0xac,0xb4,0x6d,0x6e = sqrdmulh v12.8h, v5.8h, v13.8h
21 0x23,0xb4,0xbe,0x2e = sqrdmulh v3.2s, v1.2s, v30.2s
Dneon-scalar-mul.s.cs4 0x6a,0xb5,0x6c,0x7e = sqrdmulh h10, h11, h12
5 0xb4,0xb6,0xa2,0x7e = sqrdmulh s20, s21, s2
Dneon-2velem.s.cs108 0x20,0xd0,0x62,0x0f = sqrdmulh v0.4h, v1.4h, v2.h[2]
109 0x20,0xd0,0x62,0x4f = sqrdmulh v0.8h, v1.8h, v2.h[2]
110 0x20,0xd8,0x82,0x0f = sqrdmulh v0.2s, v1.2s, v2.s[2]
111 0x20,0xd8,0x96,0x0f = sqrdmulh v0.2s, v1.2s, v22.s[2]
112 0x20,0xd8,0x82,0x4f = sqrdmulh v0.4s, v1.4s, v2.s[2]
113 0x20,0xd8,0x96,0x4f = sqrdmulh v0.4s, v1.4s, v22.s[2]
/external/llvm/test/MC/AArch64/
Dneon-scalar-by-elem-saturating-mul.s43 sqrdmulh h31, h30, v14.h[2]
44 sqrdmulh h1, h1, v1.h[4]
45 sqrdmulh h21, h22, v15.h[7]
46 sqrdmulh s5, s6, v7.s[2]
47 sqrdmulh s20, s26, v27.s[1]
Darm64-v128_lo-diagnostics.s4 sqrdmulh v0.8h, v1.8h, v16.h[0]
7 sqrdmulh h0, h1, v16.h[0]
Dneon-mul-div-instructions.s68 sqrdmulh v2.4h, v25.4h, v3.4h
69 sqrdmulh v12.8h, v5.8h, v13.8h
70 sqrdmulh v3.2s, v1.2s, v30.2s
Dneon-scalar-mul.s19 sqrdmulh h10, h11, h12
20 sqrdmulh s20, s21, s2
Dneon-2velem.s275 sqrdmulh v0.4h, v1.4h, v2.h[2]
276 sqrdmulh v0.8h, v1.8h, v2.h[2]
277 sqrdmulh v0.2s, v1.2s, v2.s[2]
278 sqrdmulh v0.2s, v1.2s, v22.s[2]
279 sqrdmulh v0.4s, v1.4s, v2.s[2]
280 sqrdmulh v0.4s, v1.4s, v22.s[2]
Dneon-diagnostics.s901 sqrdmulh h10, s11, h12
902 sqrdmulh s20, h21, s2
1261 sqrdmulh v2.2s, v25.4s, v3.4s
1262 sqrdmulh v12.16b, v5.16b, v13.16b
1263 sqrdmulh v3.4h, v1.4h, v30.2d
3671 sqrdmulh v0.4h, v1.4h, v2.h[8]
3672 sqrdmulh v0.4h, v1.4h, v16.h[2]
3673 sqrdmulh v0.8h, v1.8h, v2.h[8]
3674 sqrdmulh v0.8h, v1.8h, v16.h[2]
3675 sqrdmulh v0.2s, v1.2s, v2.s[4]
[all …]
Darm64-advsimd.s348 sqrdmulh.4h v0, v0, v0
419 ; CHECK: sqrdmulh.4h v0, v0, v0 ; encoding: [0x00,0xb4,0x60,0x2e]
1149 sqrdmulh.h h0, h0, v0[7]
1150 sqrdmulh.s s0, s0, v0[3]
1167 ; CHECK: sqrdmulh.h h0, h0, v0[7] ; encoding: [0x00,0xd8,0x70,0x5f]
1168 ; CHECK: sqrdmulh.s s0, s0, v0[3] ; encoding: [0x00,0xd8,0xa0,0x5f]
1257 sqrdmulh.4h v0, v0, v0[0]
1258 sqrdmulh.8h v0, v0, v0[1]
1259 sqrdmulh.2s v0, v0, v0[2]
1260 sqrdmulh.4s v0, v0, v0[3]
[all …]
/external/swiftshader/third_party/llvm-7.0/llvm/test/MC/Disassembler/AArch64/
Dneon-instructions.txt659 # CHECK: sqrdmulh v31.4h, v3.4h, v13.4h
660 # CHECK: sqrdmulh v0.8h, v10.8h, v20.8h
1483 # CHECK: sqrdmulh h10, h11, h12
1484 # CHECK: sqrdmulh s20, s21, s2
2455 # CHECK: sqrdmulh h7, h1, v14.h[0]
2456 # CHECK: sqrdmulh h7, h15, v8.h[1]
2457 # CHECK: sqrdmulh h7, h15, v8.h[2]
2458 # CHECK: sqrdmulh h7, h15, v8.h[3]
2459 # CHECK: sqrdmulh h7, h15, v8.h[4]
2460 # CHECK: sqrdmulh h7, h15, v8.h[5]
[all …]
/external/llvm/test/MC/Disassembler/AArch64/
Dneon-instructions.txt659 # CHECK: sqrdmulh v31.4h, v3.4h, v13.4h
660 # CHECK: sqrdmulh v0.8h, v10.8h, v20.8h
1483 # CHECK: sqrdmulh h10, h11, h12
1484 # CHECK: sqrdmulh s20, s21, s2
2455 # CHECK: sqrdmulh h7, h1, v14.h[0]
2456 # CHECK: sqrdmulh h7, h15, v8.h[1]
2457 # CHECK: sqrdmulh h7, h15, v8.h[2]
2458 # CHECK: sqrdmulh h7, h15, v8.h[3]
2459 # CHECK: sqrdmulh h7, h15, v8.h[4]
2460 # CHECK: sqrdmulh h7, h15, v8.h[5]
[all …]

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