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Searched refs:srif_regs (Results 1 – 3 of 3) sorted by relevance

/external/u-boot/arch/mips/mach-ath79/ar934x/
Dclk.c105 void __iomem *srif_regs = map_physmem(AR934X_SRIF_BASE, in ar934x_pll_init() local
114 writel(0x13210f00, srif_regs + AR934X_SRIF_CPU_DPLL2_REG); in ar934x_pll_init()
115 writel(0x03000000, srif_regs + AR934X_SRIF_CPU_DPLL3_REG); in ar934x_pll_init()
116 writel(0x13210f00, srif_regs + AR934X_SRIF_DDR_DPLL2_REG); in ar934x_pll_init()
117 writel(0x03000000, srif_regs + AR934X_SRIF_DDR_DPLL3_REG); in ar934x_pll_init()
118 writel(0x03000000, srif_regs + 0x188); /* Undocumented reg :-) */ in ar934x_pll_init()
193 ar934x_srif_pll_cfg(srif_regs + AR934X_SRIF_CPU_DPLL1_REG, cpu_srif); in ar934x_pll_init()
194 ar934x_srif_pll_cfg(srif_regs + AR934X_SRIF_DDR_DPLL1_REG, ddr_srif); in ar934x_pll_init()
/external/u-boot/arch/mips/mach-ath79/qca956x/
Dclk.c219 void __iomem *srif_regs = map_physmem(QCA956X_SRIF_BASE, in qca956x_pll_init() local
227 PLL_SRIF_DPLL2_PHASE_SHIFT_SET(6), srif_regs + QCA956X_SRIF_BB_DPLL2_REG); in qca956x_pll_init()
232 PLL_SRIF_DPLL2_PHASE_SHIFT_SET(6), srif_regs + QCA956X_SRIF_PCIE_DPLL2_REG); in qca956x_pll_init()
237 srif_regs + QCA956X_SRIF_DDR_DPLL2_REG); in qca956x_pll_init()
242 srif_regs + QCA956X_SRIF_CPU_DPLL2_REG); in qca956x_pll_init()
Dddr.c192 void __iomem *srif_regs = map_physmem(QCA956X_SRIF_BASE, QCA956X_SRIF_SIZE, in qca956x_ddr_init() local
304 writel(0x633c8176, srif_regs + QCA956X_SRIF_PMU1_REG); in qca956x_ddr_init()
307 srif_regs + QCA956X_SRIF_PMU2_REG); in qca956x_ddr_init()