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/external/swiftshader/third_party/subzero/tests_lit/llvm2ice_tests/
Dvector-select.ll59 ; MIPS32: srl [[T14]],[[T14]],0x8
63 ; MIPS32: srl [[T14]],[[T14]],0x8
67 ; MIPS32: srl [[T3]],[[T3]],0x8
70 ; MIPS32: srl [[T2]],[[T2]],0x8
80 ; MIPS32: srl [[T14]],[[T14]],0x10
84 ; MIPS32: srl [[T3]],[[T3]],0x10
87 ; MIPS32: srl [[T1]],[[T1]],0x10
96 ; MIPS32: srl [[T16:.*]],a0,0x18
98 ; MIPS32: srl [[T6]],[[T6]],0x18
99 ; MIPS32: srl [[T10]],[[T10]],0x18
[all …]
Dvector-icmp.ll660 ; MIPS32: srl [[T4]],[[T4]],0x10
663 ; MIPS32: srl [[T10:.*]],a0,0x10
664 ; MIPS32: srl [[T0]],[[T0]],0x10
671 ; MIPS32: srl [[T8]],[[T8]],0x10
682 ; MIPS32: srl [[T5]],[[T5]],0x10
685 ; MIPS32: srl [[T11:.*]],a1,0x10
686 ; MIPS32: srl [[T1]],[[T1]],0x10
693 ; MIPS32: srl [[T0]],[[T0]],0x10
704 ; MIPS32: srl [[T6]],[[T6]],0x10
707 ; MIPS32: srl [[T12:.*]],a2,0x10
[all …]
Dvector-cast.ll42 ; MIPS32: srl v0,v0,0x8
46 ; MIPS32: srl v0,v0,0x8
58 ; MIPS32: srl t2,t2,0x10
69 ; MIPS32: srl a0,a0,0x18
75 ; MIPS32: srl t2,t2,0x8
83 ; MIPS32: srl v1,v1,0x8
87 ; MIPS32: srl v1,v1,0x8
99 ; MIPS32: srl v0,v0,0x10
110 ; MIPS32: srl a1,a1,0x18
116 ; MIPS32: srl v0,v0,0x8
[all …]
Dshift.ll107 ; MIPS32: srl
118 ; MIPS32: srl
163 ; MIPS32: srl [[T1:.*]],[[VAL_LO:.*]],0x1c
201 ; MIPS32: srl [[T2:.*]],{{.*}},0x1
203 ; MIPS32: srl {{.*}},[[VAL_HI]],0x1
215 ; MIPS32: srl [[T2:.*]],{{.*}},0x4
217 ; MIPS32: srl {{.*}},[[VAL_HI]],0x4
241 ; MIPS32: srl {{.*}},{{.*}},0x8
254 ; MIPS32: srl [[T2:.*]],{{.*}},0x1
268 ; MIPS32: srl [[T2:.*]],{{.*}},0x4
/external/swiftshader/third_party/llvm-7.0/llvm/test/MC/Mips/
Drotations32.s24 # CHECK-32: srl $4, $4, 0 # encoding: [0x00,0x04,0x20,0x02]
27 # CHECK-32: srl $4, $5, 0 # encoding: [0x00,0x05,0x20,0x02]
31 # CHECK-32: srl $4, $4, 31 # encoding: [0x00,0x04,0x27,0xc2]
36 # CHECK-32: srl $4, $5, 31 # encoding: [0x00,0x05,0x27,0xc2]
41 # CHECK-32: srl $4, $4, 30 # encoding: [0x00,0x04,0x27,0x82]
46 # CHECK-32: srl $4, $5, 30 # encoding: [0x00,0x05,0x27,0x82]
63 # CHECK-32: srl $4, $4, 0 # encoding: [0x00,0x04,0x20,0x02]
66 # CHECK-32: srl $4, $5, 0 # encoding: [0x00,0x05,0x20,0x02]
69 # CHECK-32: srl $1, $4, 1 # encoding: [0x00,0x04,0x08,0x42]
74 # CHECK-32: srl $1, $5, 1 # encoding: [0x00,0x05,0x08,0x42]
[all …]
Dmicromips-shift-instructions.s14 # CHECK-EL: srl $4, $3, 7 # encoding: [0x83,0x00,0x40,0x38]
26 # CHECK-EL: srl $3, $3, 7 # encoding: [0x63,0x00,0x40,0x38]
34 # CHECK-EB: srl $4, $3, 7 # encoding: [0x00,0x83,0x38,0x40]
46 # CHECK-EB: srl $3, $3, 7 # encoding: [0x00,0x63,0x38,0x40]
51 srl $4, $3, 7
57 srl $2, $3, $5
60 srl $2, $3
63 srl $3, 7
Drotations64.s24 # CHECK-64: srl $4, $4, 0 # encoding: [0x00,0x04,0x20,0x02]
27 # CHECK-64: srl $4, $5, 0 # encoding: [0x00,0x05,0x20,0x02]
31 # CHECK-64: srl $4, $4, 31 # encoding: [0x00,0x04,0x27,0xc2]
36 # CHECK-64: srl $4, $5, 31 # encoding: [0x00,0x05,0x27,0xc2]
41 # CHECK-64: srl $4, $4, 30 # encoding: [0x00,0x04,0x27,0x82]
46 # CHECK-64: srl $4, $5, 30 # encoding: [0x00,0x05,0x27,0x82]
63 # CHECK-64: srl $4, $4, 0 # encoding: [0x00,0x04,0x20,0x02]
66 # CHECK-64: srl $4, $5, 0 # encoding: [0x00,0x05,0x20,0x02]
69 # CHECK-64: srl $1, $4, 1 # encoding: [0x00,0x04,0x08,0x42]
74 # CHECK-64: srl $1, $5, 1 # encoding: [0x00,0x05,0x08,0x42]
[all …]
Dmips-expansions.s788 # CHECK-BE: srl $1, $8, 8 # encoding: [0x00,0x08,0x0a,0x02]
791 # CHECK-LE: srl $1, $8, 8 # encoding: [0x02,0x0a,0x08,0x00]
796 # CHECK-BE: srl $1, $8, 8 # encoding: [0x00,0x08,0x0a,0x02]
799 # CHECK-LE: srl $1, $8, 8 # encoding: [0x02,0x0a,0x08,0x00]
807 # CHECK-BE: srl $8, $8, 8 # encoding: [0x00,0x08,0x42,0x02]
815 # CHECK-LE: srl $8, $8, 8 # encoding: [0x02,0x42,0x08,0x00]
823 # CHECK-BE: srl $1, $8, 8 # encoding: [0x00,0x08,0x0a,0x02]
826 # CHECK-LE: srl $1, $8, 8 # encoding: [0x02,0x0a,0x08,0x00]
834 # CHECK-BE: srl $8, $8, 8 # encoding: [0x00,0x08,0x42,0x02]
842 # CHECK-LE: srl $8, $8, 8 # encoding: [0x02,0x42,0x08,0x00]
[all …]
/external/llvm/test/MC/Mips/
Drotations32.s24 # CHECK-32: srl $4, $4, 0 # encoding: [0x00,0x04,0x20,0x02]
27 # CHECK-32: srl $4, $5, 0 # encoding: [0x00,0x05,0x20,0x02]
31 # CHECK-32: srl $4, $4, 31 # encoding: [0x00,0x04,0x27,0xc2]
36 # CHECK-32: srl $4, $5, 31 # encoding: [0x00,0x05,0x27,0xc2]
41 # CHECK-32: srl $4, $4, 30 # encoding: [0x00,0x04,0x27,0x82]
46 # CHECK-32: srl $4, $5, 30 # encoding: [0x00,0x05,0x27,0x82]
63 # CHECK-32: srl $4, $4, 0 # encoding: [0x00,0x04,0x20,0x02]
66 # CHECK-32: srl $4, $5, 0 # encoding: [0x00,0x05,0x20,0x02]
69 # CHECK-32: srl $1, $4, 1 # encoding: [0x00,0x04,0x08,0x42]
74 # CHECK-32: srl $1, $5, 1 # encoding: [0x00,0x05,0x08,0x42]
[all …]
Dmicromips-shift-instructions.s14 # CHECK-EL: srl $4, $3, 7 # encoding: [0x83,0x00,0x40,0x38]
26 # CHECK-EL: srl $3, $3, 7 # encoding: [0x63,0x00,0x40,0x38]
34 # CHECK-EB: srl $4, $3, 7 # encoding: [0x00,0x83,0x38,0x40]
46 # CHECK-EB: srl $3, $3, 7 # encoding: [0x00,0x63,0x38,0x40]
51 srl $4, $3, 7
57 srl $2, $3, $5
60 srl $2, $3
63 srl $3, 7
Drotations64.s24 # CHECK-64: srl $4, $4, 0 # encoding: [0x00,0x04,0x20,0x02]
27 # CHECK-64: srl $4, $5, 0 # encoding: [0x00,0x05,0x20,0x02]
31 # CHECK-64: srl $4, $4, 31 # encoding: [0x00,0x04,0x27,0xc2]
36 # CHECK-64: srl $4, $5, 31 # encoding: [0x00,0x05,0x27,0xc2]
41 # CHECK-64: srl $4, $4, 30 # encoding: [0x00,0x04,0x27,0x82]
46 # CHECK-64: srl $4, $5, 30 # encoding: [0x00,0x05,0x27,0x82]
63 # CHECK-64: srl $4, $4, 0 # encoding: [0x00,0x04,0x20,0x02]
66 # CHECK-64: srl $4, $5, 0 # encoding: [0x00,0x05,0x20,0x02]
69 # CHECK-64: srl $1, $4, 1 # encoding: [0x00,0x04,0x08,0x42]
74 # CHECK-64: srl $1, $5, 1 # encoding: [0x00,0x05,0x08,0x42]
[all …]
/external/llvm/test/CodeGen/AMDGPU/
Dshift-and-i64-ubfe.ll16 %srl = lshr i64 %ld.64, 31
17 %bit = and i64 %srl, 1
33 %srl = lshr i64 %ld.64, 63
34 %bit = and i64 %srl, 1
49 %srl = lshr i64 %ld.64, 1
50 %bit = and i64 %srl, 1
65 %srl = lshr i64 %ld.64, 20
66 %bit = and i64 %srl, 1
81 %srl = lshr i64 %ld.64, 32
82 %bit = and i64 %srl, 1
[all …]
Dshift-and-i128-ubfe.ll19 %srl = lshr i128 %ld.64, 31
20 %bit = and i128 %srl, 1
41 %srl = lshr i128 %ld.64, 63
42 %bit = and i128 %srl, 1
63 %srl = lshr i128 %ld.64, 95
64 %bit = and i128 %srl, 1
85 %srl = lshr i128 %ld.64, 127
86 %bit = and i128 %srl, 1
109 %srl = lshr i128 %ld.64, 34
110 %bit = and i128 %srl, 73786976294838206463
/external/swiftshader/third_party/llvm-7.0/llvm/test/CodeGen/AMDGPU/
Dshift-and-i64-ubfe.ll17 %srl = lshr i64 %ld.64, 31
18 %bit = and i64 %srl, 1
35 %srl = lshr i64 %ld.64, 63
36 %bit = and i64 %srl, 1
51 %srl = lshr i64 %ld.64, 1
52 %bit = and i64 %srl, 1
67 %srl = lshr i64 %ld.64, 20
68 %bit = and i64 %srl, 1
84 %srl = lshr i64 %ld.64, 32
85 %bit = and i64 %srl, 1
[all …]
Dshift-and-i128-ubfe.ll19 %srl = lshr i128 %ld.64, 31
20 %bit = and i128 %srl, 1
42 %srl = lshr i128 %ld.64, 63
43 %bit = and i128 %srl, 1
64 %srl = lshr i128 %ld.64, 95
65 %bit = and i128 %srl, 1
87 %srl = lshr i128 %ld.64, 127
88 %bit = and i128 %srl, 1
111 %srl = lshr i128 %ld.64, 34
112 %bit = and i128 %srl, 73786976294838206463
/external/swiftshader/third_party/llvm-7.0/llvm/test/CodeGen/SystemZ/
Dshift-02.ll8 ; CHECK: srl %r2, 1
17 ; CHECK: srl %r2, 31
26 ; CHECK-NOT: srl %r2, 32
35 ; CHECK-NOT: srl %r2, -1{{.*}}
45 ; CHECK: srl %r2, 0(%r3)
54 ; CHECK: srl %r2, 10(%r3)
64 ; CHECK: srl %r2, 10(%r3)
76 ; CHECK: srl %r2, 4095(%r3)
87 ; CHECK: srl %r2, 0(%r3)
98 ; CHECK: srl %r2, 0({{%r[34]}})
[all …]
Dsetcc-02.ll11 ; CHECK-NEXT: srl %r2, 31
24 ; CHECK-NEXT: srl %r2, 31
36 ; CHECK-NEXT: srl %r2, 31
49 ; CHECK-NEXT: srl %r2, 31
85 ; CHECK-NEXT: srl %r2, 31
97 ; CHECK-NEXT: srl %r2, 31
133 ; CHECK-NEXT: srl %r2, 31
157 ; CHECK-NEXT: srl %r2, 31
169 ; CHECK-NEXT: srl %r2, 31
/external/llvm/test/CodeGen/SystemZ/
Dshift-02.ll8 ; CHECK: srl %r2, 1
17 ; CHECK: srl %r2, 31
26 ; CHECK-NOT: srl %r2, 32
35 ; CHECK-NOT: srl %r2, -1{{.*}}
45 ; CHECK: srl %r2, 0(%r3)
54 ; CHECK: srl %r2, 10(%r3)
64 ; CHECK: srl %r2, 10(%r3)
76 ; CHECK: srl %r2, 4095(%r3)
87 ; CHECK: srl %r2, 0(%r3)
98 ; CHECK: srl %r2, 0({{%r[34]}})
[all …]
Dsetcc-02.ll11 ; CHECK-NEXT: srl %r2, 31
24 ; CHECK-NEXT: srl %r2, 31
36 ; CHECK-NEXT: srl %r2, 31
49 ; CHECK-NEXT: srl %r2, 31
85 ; CHECK-NEXT: srl %r2, 31
97 ; CHECK-NEXT: srl %r2, 31
133 ; CHECK-NEXT: srl %r2, 31
157 ; CHECK-NEXT: srl %r2, 31
169 ; CHECK-NEXT: srl %r2, 31
/external/swiftshader/third_party/llvm-7.0/llvm/test/TableGen/
Darithmetic.td10 // CHECK: bits<8> srl = { 0, 0, 0, 1, 1, 1, 1, 1 };
20 bits<8> srl = !srl(a, b);
/external/llvm/test/CodeGen/Mips/
Dbswap.ll16 ; MIPS16-DAG: srl $[[R0:[0-9]+]], $4, 8
17 ; MIPS16-DAG: srl $[[R1:[0-9]+]], $4, 24
45 ; MIPS16-DAG: srl $[[R0:[0-9]+]], $5, 8
46 ; MIPS16-DAG: srl $[[R1:[0-9]+]], $5, 24
56 ; MIPS16-DAG: srl $[[R0:[0-9]+]], $4, 8
57 ; MIPS16-DAG: srl $[[R1:[0-9]+]], $4, 24
/external/swiftshader/third_party/llvm-7.0/llvm/test/CodeGen/X86/
Dcombine-srl.ll6 ; fold (srl 0, x) -> 0
21 ; fold (srl x, c >= size(x)) -> undef
38 ; fold (srl x, 0) -> x
47 ; if (srl x, c) is known to be zero, return 0
90 ; fold (srl (srl x, c1), c2) -> (srl x, (add c1, c2))
130 ; fold (srl (srl x, c1), c2) -> 0
161 ; fold (srl (trunc (srl x, c1)), c2) -> (trunc (srl x, (add c1, c2)))
230 ; fold (srl (trunc (srl x, c1)), c2) -> 0
285 ; fold (srl (shl x, c), c) -> (and x, cst2)
317 ; fold (srl (sra X, Y), 31) -> (srl X, 31)
[all …]
/external/swiftshader/third_party/llvm-7.0/llvm/test/CodeGen/Mips/
Dbswap.ll21 ; MIPS16-DAG: srl $[[R0:[0-9]+]], $4, 8
22 ; MIPS16-DAG: srl $[[R1:[0-9]+]], $4, 24
56 ; MIPS16-DAG: srl $[[R0:[0-9]+]], $5, 8
57 ; MIPS16-DAG: srl $[[R1:[0-9]+]], $5, 24
67 ; MIPS16-DAG: srl $[[R0:[0-9]+]], $4, 8
68 ; MIPS16-DAG: srl $[[R1:[0-9]+]], $4, 24
/external/swiftshader/third_party/llvm-7.0/llvm/test/CodeGen/Mips/msa/
Dshift-dagcombine.ll31 ; CHECK-NOT: srl
33 ; CHECK-NOT: srl
39 ; CHECK-NOT: srl
42 ; CHECK-NOT: srl
/external/llvm/test/CodeGen/Mips/msa/
Dshift-dagcombine.ll31 ; CHECK-NOT: srl
33 ; CHECK-NOT: srl
39 ; CHECK-NOT: srl
42 ; CHECK-NOT: srl

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