/external/swiftshader/third_party/llvm-7.0/llvm/test/CodeGen/AMDGPU/ |
D | rename-independent-subregs.mir | 9 # can be moved to a new virtual register. The third def of sub1 however is used 13 # CHECK: S_NOP 0, implicit-def undef %2.sub1 14 # CHECK: S_NOP 0, implicit %2.sub1 15 # CHECK: S_NOP 0, implicit-def undef %1.sub1 16 # CHECK: S_NOP 0, implicit %1.sub1 17 # CHECK: S_NOP 0, implicit-def %0.sub1 25 S_NOP 0, implicit-def %0.sub1 26 S_NOP 0, implicit %0.sub1 27 S_NOP 0, implicit-def %0.sub1 28 S_NOP 0, implicit %0.sub1 [all …]
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D | detect-dead-lanes.mir | 9 # CHECK: %3:sreg_128 = REG_SEQUENCE %0, %subreg.sub0, %1, %subreg.sub1, undef %2, %subreg.sub3 11 # CHECK: S_NOP 0, implicit %3.sub1 16 # CHECK: S_NOP 0, implicit %4.sub1 31 %3 = REG_SEQUENCE %0, %subreg.sub0, %1, %subreg.sub1, %2, %subreg.sub3 33 S_NOP 0, implicit %3.sub1 38 S_NOP 0, implicit %4.sub1 49 # CHECK: S_NOP 0, implicit undef %1.sub1 53 # CHECK: S_NOP 0, implicit undef %2.sub1 58 # CHECK: S_NOP 0, implicit undef %4.sub1 64 # CHECK: %7:sreg_32_xm0 = EXTRACT_SUBREG %5, %subreg.sub1 [all …]
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D | rename-independent-subregs-mac-operands.mir | 54 %13.sub1 = COPY %8 62 %14 = COPY %1.sub1 65 %15.sub1 = COPY killed %14 76 # GCN: undef %8.sub1:vreg_128 = V_MAC_F32_e32 undef %2:vgpr_32, undef %1:vgpr_32, undef %8.sub1, im… 82 # GCN: %8.sub1:vreg_128 = V_ADD_F32_e32 %8.sub1, %8.sub1, implicit $exec 86 # GCN: BUFFER_STORE_DWORD_OFFEN %8.sub1, %0, 113 undef %6.sub1 = V_MAC_F32_e32 undef %2, undef %1, undef %6.sub1, implicit $exec 124 %6.sub1 = V_ADD_F32_e32 %6.sub1, %6.sub1, implicit $exec 130 … BUFFER_STORE_DWORD_OFFEN %6.sub1, %0, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr4, 4, 0, 0, 0, implicit $exec 141 # GCN-NEXT: dead undef %3.sub1:vreg_128 = COPY %2.sub0 [all …]
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D | spill-empty-live-interval.mir | 10 # CHECK: undef %7.sub1:vreg_64 = V_MAC_F32_e32 0, undef %1:vgpr_32, undef %7.sub1, implicit $exec 12 # CHECK-NEXT: undef %5.sub1:vreg_64 = V_MOV_B32_e32 1786773504, implicit $exec 13 # CHECK-NEXT: dead %2:vgpr_32 = V_MUL_F32_e32 0, %5.sub1, implicit $exec 15 # CHECK: S_NOP 0, implicit %6.sub1 17 # CHECK-NEXT: S_NOP 0, implicit %8.sub1 30 undef %0.sub1 = V_MAC_F32_e32 0, undef %1, undef %0.sub1, implicit $exec 31 undef %3.sub1 = V_MOV_B32_e32 1786773504, implicit $exec 32 dead %2 = V_MUL_F32_e32 0, %3.sub1, implicit $exec 35 S_NOP 0, implicit %3.sub1 36 S_NOP 0, implicit %0.sub1
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D | opt-sgpr-to-vgpr-copy.mir | 8 …GPR_PAIR:[0-9]+]]:sreg_64 = REG_SEQUENCE killed %[[LO]], %subreg.sub0, killed %[[HI]], %subreg.sub1 15 …GPR_PAIR:[0-9]+]]:sreg_64 = REG_SEQUENCE killed %[[LO]], %subreg.sub0, killed %[[HI]], %subreg.sub1 20 …:[0-9]+]]:vreg_64 = REG_SEQUENCE killed %{{[0-9]+}}, %subreg.sub0, killed %{{[0-9]+}}, %subreg.sub1 112 %10 = REG_SEQUENCE %2, %subreg.sub0, killed %9, %subreg.sub1 115 %12 = COPY %10.sub1 117 %14 = COPY %8.sub1 120 %17 = REG_SEQUENCE killed %15, %subreg.sub0, killed %16, %subreg.sub1 123 %20 = REG_SEQUENCE killed %19, %subreg.sub0, killed %18, %subreg.sub1 136 %27 = REG_SEQUENCE killed %26, %subreg.sub0, killed %25, %subreg.sub1 211 %11 = REG_SEQUENCE %2, %subreg.sub0, killed %10, %subreg.sub1 [all …]
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D | flat-load-clustering.mir | 62 %11 = COPY %4.sub1 63 %12.sub1 = V_ADDC_U32_e32 %11, %2, implicit-def dead $vcc, implicit killed $vcc, implicit $exec 66 %8 = COPY %3.sub1 67 %9.sub1 = V_ADDC_U32_e32 %8, %2, implicit-def dead $vcc, implicit killed $vcc, implicit $exec 69 …%13.sub1 = V_ADDC_U32_e32 %12.sub1, %2, implicit-def dead $vcc, implicit killed $vcc, implicit $ex… 72 …%10.sub1 = V_ADDC_U32_e32 %9.sub1, %2, implicit-def dead $vcc, implicit killed $vcc, implicit $exec
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D | sched-crash-dbg-value.mir | 210 %12:sreg_32_xm0 = S_MUL_I32 %11, %10.sub1 212 %14:vgpr_32 = V_MUL_LO_I32 %1, %10.sub1, implicit $exec 224 %27.sub1:sreg_64_xexec = S_MOV_B32 0 227 %29.sub1:sreg_64 = S_ADDC_U32 %5.sub1, %28.sub1, implicit-def dead $scc, implicit killed $scc 232 %33:sgpr_32 = S_ADDC_U32 %5.sub1, %31.sub1, implicit-def dead $scc, implicit killed $scc 236 undef %38.sub1:vreg_64 = V_ASHRREV_I32_e32 31, %37.sub0, implicit $exec 241 %40.sub1:vreg_64, dead %43:sreg_64_xexec = V_ADDC_U32_e64 %42, %39.sub1, %41, implicit $exec 243 undef %45.sub1:vreg_64 = IMPLICIT_DEF 244 %45.sub0:vreg_64 = COPY %37.sub1 248 %47.sub1:vreg_64, dead %50:sreg_64_xexec = V_ADDC_U32_e64 %49, %46.sub1, %48, implicit $exec [all …]
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D | twoaddr-mad.mir | 16 %1 = COPY %0.sub1 35 %1 = COPY %0.sub1 42 # GCN: V_MADAK_F32 killed %0.sub0, %0.sub1, 1078523331, implicit $exec 54 %2 = V_MAC_F32_e32 killed %0.sub0, %0.sub1, %1, implicit $exec 71 %1 = COPY %0.sub1 90 %1 = COPY %0.sub1 97 # GCN: V_MADAK_F16 killed %0.sub0, %0.sub1, 1078523331, implicit $exec 109 %2 = V_MAC_F16_e32 killed %0.sub0, %0.sub1, %1, implicit $exec
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D | regcoalesce-prune.mir | 13 undef %5.sub1 = V_MOV_B32_e32 0, implicit $exec 20 %0.sub1 = COPY %1 26 %2 : vgpr_32 = V_CVT_F32_I32_e32 killed %5.sub1, implicit $exec 29 %3 : vgpr_32 = V_CVT_F32_I32_e32 killed %6.sub1, implicit $exec
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D | subreg-split-live-in-error.mir | 28 # undef %0.sub0:vreg_64 = COPY %123:sreg_32 ; undef point for %0.sub1 58 %3.sub1:vreg_128 = COPY %3.sub0 69 %3.sub1:vreg_128 = COPY %3.sub0 87 undef %9.sub1:vreg_64 = V_MUL_F32_e32 0, %1, implicit $exec 90 %11.sub1:sreg_256 = COPY %11.sub0 106 %15.sub1:vreg_128 = COPY %15.sub0 118 %15.sub1:vreg_128 = COPY %15.sub0 125 %15.sub1:vreg_128 = COPY %15.sub0 158 …%25:vgpr_32 = V_MUL_F32_e64 0, target-flags(amdgpu-gotprel32-lo) 0, 0, %20.sub1, 0, 0, implicit $e… 213 …%52:vgpr_32 = V_MAD_F32 0, %3.sub1, 0, target-flags(amdgpu-gotprel32-lo) 0, 1, %3.sub0, 0, 0, impl… [all …]
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/external/llvm/test/CodeGen/AMDGPU/ |
D | rename-independent-subregs.mir | 7 # can be moved to a new virtual register. The third def of sub1 however is used 11 # CHECK: S_NOP 0, implicit-def undef %2:sub1 12 # CHECK: S_NOP 0, implicit %2:sub1 13 # CHECK: S_NOP 0, implicit-def undef %1:sub1 14 # CHECK: S_NOP 0, implicit %1:sub1 15 # CHECK: S_NOP 0, implicit-def %0:sub1 24 S_NOP 0, implicit-def %0:sub1 25 S_NOP 0, implicit %0:sub1 26 S_NOP 0, implicit-def %0:sub1 27 S_NOP 0, implicit %0:sub1 [all …]
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D | detect-dead-lanes.mir | 21 # CHECK: S_NOP 0, implicit %3:sub1 26 # CHECK: S_NOP 0, implicit %4:sub1 42 %3 = REG_SEQUENCE %0, %subreg.sub0, %1, %subreg.sub1, %2, %subreg.sub3 44 S_NOP 0, implicit %3:sub1 49 S_NOP 0, implicit %4:sub1 60 # CHECK: S_NOP 0, implicit undef %1:sub1 64 # CHECK: S_NOP 0, implicit undef %2:sub1 69 # CHECK: S_NOP 0, implicit undef %4:sub1 106 S_NOP 0, implicit %1:sub1 110 S_NOP 0, implicit %2:sub1 [all …]
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/external/snakeyaml/src/test/java/org/yaml/snakeyaml/ruby/ |
D | TestObject.java | 19 private Sub1 sub1; field in TestObject 23 return sub1; in getSub1() 26 public void setSub1(Sub1 sub1) { in setSub1() argument 27 this.sub1 = sub1; in setSub1()
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/external/icu/icu4j/main/classes/core/src/com/ibm/icu/text/ |
D | NFRule.java | 104 private NFSubstitution sub1 = null; field in NFRule 418 sub1 = extractSubstitution(owner, predecessor); in extractSubstitutions() 419 if (sub1 == null) { in extractSubstitutions() 539 if (sub1 != null) { in setBaseValue() 540 sub1.setDivisor(radix, exponent); in setBaseValue() 622 && Objects.equals(sub1, that2.sub1) in equals() 683 if (ruleText.startsWith(" ") && (sub1 == null || sub1.getPos() != 0)) { in toString() 693 if (sub1 != null) { in toString() 694 ruleTextCopy.insert(sub1.getPos(), sub1.toString()); in toString() 773 if (sub1 != null) { in doFormat() [all …]
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/external/icu/android_icu4j/src/main/java/android/icu/text/ |
D | NFRule.java | 105 private NFSubstitution sub1 = null; field in NFRule 419 sub1 = extractSubstitution(owner, predecessor); in extractSubstitutions() 420 if (sub1 == null) { in extractSubstitutions() 540 if (sub1 != null) { in setBaseValue() 541 sub1.setDivisor(radix, exponent); in setBaseValue() 623 && Objects.equals(sub1, that2.sub1) in equals() 684 if (ruleText.startsWith(" ") && (sub1 == null || sub1.getPos() != 0)) { in toString() 694 if (sub1 != null) { in toString() 695 ruleTextCopy.insert(sub1.getPos(), sub1.toString()); in toString() 774 if (sub1 != null) { in doFormat() [all …]
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/external/tensorflow/tensorflow/lite/micro/tools/make/ |
D | merge_arduino_zips_test.sh | 25 mkdir ${INPUT1_DIR}/sub1/ 26 touch ${INPUT1_DIR}/sub1/c.txt 38 mkdir ${INPUT2_DIR}/sub1/ 39 touch ${INPUT2_DIR}/sub1/f.txt 61 for EXPECTED_FILE in a.txt b.txt sub1/c.txt sub2/d.txt e.txt sub1/f.txt sub3/g.txt
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/external/icu/icu4c/source/i18n/ |
D | nfrule.cpp | 43 , sub1(NULL) in NFRule() 55 if (sub1 != sub2) { in ~NFRule() 59 delete sub1; in ~NFRule() 60 sub1 = NULL; in ~NFRule() 422 sub1 = extractSubstitution(ruleSet, predecessor, status); in extractSubstitutions() 423 if (sub1 == NULL) { in extractSubstitutions() 552 if (sub1 != NULL) { in setBaseValue() 553 sub1->setDivisor(radix, exponent, status); in setBaseValue() 617 util_equalSubstitutions(const NFSubstitution* sub1, const NFSubstitution* sub2) in util_equalSubstitutions() argument 619 if (sub1) { in util_equalSubstitutions() [all …]
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/external/perfetto/src/protozero/test/ |
D | cppgen_conformance_unittest.cc | 163 auto* sub1 = i == 0 ? msg_v2.mutable_sub1() : msg_v2.add_sub1_rep(); in TEST() local 164 sub1->set_sub1_int(12); in TEST() 165 sub1->set_sub1_string("sub1-string"); in TEST() 166 sub1->set_sub1_int_v2(13); in TEST() 167 sub1->set_sub1_string_v2("sub1-string-v2"); in TEST() 212 auto* sub1 = i == 0 ? &msg_v1.sub1() : &msg_v1.sub1_rep()[i - 1]; in TEST() local 213 EXPECT_EQ(sub1->sub1_int(), 12); in TEST() 214 EXPECT_EQ(sub1->sub1_string(), "sub1-string"); in TEST() 245 auto* sub1 = i == 0 ? &msg_v2.sub1() : &msg_v2.sub1_rep()[i - 1]; in TEST() local 246 EXPECT_EQ(sub1->sub1_int(), 12); in TEST() [all …]
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/external/smali/dexlib2/src/test/java/org/jf/dexlib2/analysis/ |
D | CommonSuperclassTest.java | 206 String sub1 = "Liface/sub1;"; in testGetCommonSuperclass_interfaces() local 222 superclassTest(base1, base1, sub1); in testGetCommonSuperclass_interfaces() 235 superclassTest(unknown, sub1, iface1); in testGetCommonSuperclass_interfaces() 237 superclassTest(base2, base2, sub1); in testGetCommonSuperclass_interfaces() 245 superclassTest(sub1, sub1, classsub1); in testGetCommonSuperclass_interfaces() 248 superclassTest(sub1, sub1, classsub2); in testGetCommonSuperclass_interfaces() 255 superclassTest(object, sub1, classsub4); in testGetCommonSuperclass_interfaces() 257 superclassTest(sub1, sub2, sub1); in testGetCommonSuperclass_interfaces() 259 superclassTest(sub1, sub1, classsub1234); in testGetCommonSuperclass_interfaces()
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/external/swiftshader/third_party/llvm-7.0/llvm/test/CodeGen/AMDGPU/GlobalISel/ |
D | inst-select-load-smrd.mir | 47 # SIVI: [[K:%[0-9]+]]:sreg_64 = REG_SEQUENCE [[K_LO]], %subreg.sub0, [[K_HI]], %subreg.sub1 51 # SIVI-DAG: [[K_SUB1:%[0-9]+]]:sgpr_32 = COPY [[K]].sub1 52 # SIVI-DAG: [[PTR_HI:%[0-9]+]]:sgpr_32 = COPY [[PTR]].sub1 54 …ADD_PTR:%[0-9]+]]:sreg_64 = REG_SEQUENCE [[ADD_PTR_LO]], %subreg.sub0, [[ADD_PTR_HI]], %subreg.sub1 61 # GCN: [[K:%[0-9]+]]:sreg_64 = REG_SEQUENCE [[K_LO]], %subreg.sub0, [[K_HI]], %subreg.sub1 65 # GCN-DAG: [[K_SUB1:%[0-9]+]]:sgpr_32 = COPY [[K]].sub1 66 # GCN-DAG: [[PTR_HI:%[0-9]+]]:sgpr_32 = COPY [[PTR]].sub1 68 …ADD_PTR:%[0-9]+]]:sreg_64 = REG_SEQUENCE [[ADD_PTR_LO]], %subreg.sub0, [[ADD_PTR_HI]], %subreg.sub1 79 # SIVI: [[K:%[0-9]+]]:sreg_64 = REG_SEQUENCE [[K_LO]], %subreg.sub0, [[K_HI]], %subreg.sub1 83 # SIVI-DAG: [[K_SUB1:%[0-9]+]]:sgpr_32 = COPY [[K]].sub1 [all …]
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/external/tensorflow/tensorflow/python/kernel_tests/distributions/ |
D | kullback_leibler_test.py | 131 sub1 = Sub1(loc=0.0, scale=1.0) 135 self.assertEqual("sub1-1", fn(sub1, sub1)) 136 self.assertEqual("sub1-2", fn(sub1, sub2)) 137 self.assertEqual("sub2-1", fn(sub2, sub1)) 139 self.assertEqual("sub1-1", fn(sub11, sub1)) 141 self.assertEqual("sub1-1", fn(sub11, sub1)) 144 self.assertEqual("sub1-1", fn(sub1, sub11))
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/external/llvm/test/Transforms/InstCombine/ |
D | phi-preserve-ir-flags.ll | 15 %sub1 = fsub fast float %a, %c 23 %e = phi float [ %sub0, %cond.true ], [ %sub1, %cond.false ] 37 %sub1 = fsub float %a, %c 45 %e = phi float [ %sub0, %cond.true ], [ %sub1, %cond.false ] 59 %sub1 = fsub fast float %b, 2.0 66 %e = phi float [ %sub0, %cond.true ], [ %sub1, %cond.false ] 80 %sub1 = fsub float %b, 2.0 87 %e = phi float [ %sub0, %cond.true ], [ %sub1, %cond.false ]
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D | fmul.ll | 25 %sub1 = fsub float -0.000000e+00, %x 27 %mul = fmul fast float %sub1, %sub2 35 %sub1 = fsub nsz float 0.000000e+00, %x 37 %mul = fmul float %sub1, %sub2 45 %sub1 = fsub float -0.000000e+00, %x 46 %mul = fmul float %sub1, %y 55 %sub1 = fsub nsz float 0.000000e+00, %x 56 %mul = fmul float %sub1, %y 66 %sub1 = fsub float -0.000000e+00, %x 67 %mul = fmul float %sub1, %y [all …]
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/external/swiftshader/third_party/llvm-7.0/llvm/test/Transforms/InstCombine/ |
D | phi-preserve-ir-flags.ll | 15 %sub1 = fsub fast float %a, %c 23 %e = phi float [ %sub0, %cond.true ], [ %sub1, %cond.false ] 37 %sub1 = fsub float %a, %c 45 %e = phi float [ %sub0, %cond.true ], [ %sub1, %cond.false ] 59 %sub1 = fsub fast float %b, 2.0 66 %e = phi float [ %sub0, %cond.true ], [ %sub1, %cond.false ] 80 %sub1 = fsub float %b, 2.0 87 %e = phi float [ %sub0, %cond.true ], [ %sub1, %cond.false ]
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/external/sfntly/cpp/src/test/ |
D | bitmap_table_test.cc | 89 IndexSubTablePtr sub1 = strike4->GetIndexSubTable(0); in CommonReadingTest() local 90 EXPECT_FALSE(sub1 == NULL); in CommonReadingTest() 91 EXPECT_EQ(sub1->image_format(), STRIKE4_SUB1_IMAGE_FORMAT); in CommonReadingTest() 92 EXPECT_EQ(sub1->first_glyph_index(), STRIKE1_START_GLYPH_INDEX); in CommonReadingTest() 93 EXPECT_EQ(sub1->last_glyph_index(), STRIKE1_END_GLYPH_INDEX); in CommonReadingTest() 94 EXPECT_EQ(sub1->image_data_offset(), STRIKE4_SUB1_IMAGE_DATA_OFFSET); in CommonReadingTest() 97 EXPECT_EQ(sub1->GlyphOffset(i), STRIKE4_SUB1_GLYPH_OFFSET[i]); in CommonReadingTest() 113 IndexSubTablePtr sub1 = strike4->GetIndexSubTable(0); in TestReadingBitmapTable() local 116 EXPECT_EQ(sub1->index_format(), STRIKE4_SUB1_INDEX_FORMAT); in TestReadingBitmapTable()
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