Searched refs:sube (Results 1 – 25 of 34) sorted by relevance
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3 ; When a i64 sub is expanded to subc + sube.10 ; sube22 ; sube24 ; However since subc and sube are "glued" together, this ends up being a25 ; cycle when the scheduler combine subc and sube as a single scheduling30 ; fix subc / sube (and addc / adde) to use physical register dependency instead.
52 sube=" \"@" # Substitute end843 deflt = " " subs substr(deflt, 3) sube864 print def i, subs "PNG_" i sube end >out868 print def i, subs "PNG_set_" i sube end >out
870 [(set GR8:$dst, (sube GR8:$src, GR8:$src2)),875 [(set GR16:$dst, (sube GR16:$src, GR16:$src2)),881 [(set GR8:$dst, (sube GR8:$src, imm:$src2)),886 [(set GR16:$dst, (sube GR16:$src, imm:$src2)),892 [(set GR8:$dst, (sube GR8:$src, (load addr:$src2))),897 [(set GR16:$dst, (sube GR16:$src, (load addr:$src2))),904 [(store (sube (load addr:$dst), GR8:$src), addr:$dst),909 [(store (sube (load addr:$dst), GR16:$src), addr:$dst),915 [(store (sube (load addr:$dst), (i8 imm:$src)), addr:$dst),920 [(store (sube (load addr:$dst), (i16 imm:$src)), addr:$dst),[all …]
878 [(set GR8:$dst, (sube GR8:$src, GR8:$src2)),883 [(set GR16:$dst, (sube GR16:$src, GR16:$src2)),889 [(set GR8:$dst, (sube GR8:$src, imm:$src2)),894 [(set GR16:$dst, (sube GR16:$src, imm:$src2)),900 [(set GR8:$dst, (sube GR8:$src, (load addr:$src2))),905 [(set GR16:$dst, (sube GR16:$src, (load addr:$src2))),912 [(store (sube (load addr:$dst), GR8:$src), addr:$dst),917 [(store (sube (load addr:$dst), GR16:$src), addr:$dst),923 [(store (sube (load addr:$dst), (i8 imm:$src)), addr:$dst),928 [(store (sube (load addr:$dst), (i16 imm:$src)), addr:$dst),[all …]
250 sube=8838 key
367 defm SUBB_ : ALUarith<0b011, "subb", sube, i32lo16z, i32hi16>;373 def : Pat<(sube GPR:$Rs1, i32lo16z:$imm),379 def : Pat<(sube GPR:$Rs1, i32hi16:$imm),393 defm SUBB_F_ : ALUarith<0b011, "subb.f", sube, i32lo16z, i32hi16>;
369 defm SUBB_ : ALUarith<0b011, "subb", sube, i32lo16z, i32hi16>;375 def : Pat<(sube GPR:$Rs1, i32lo16z:$imm),381 def : Pat<(sube GPR:$Rs1, i32hi16:$imm),395 defm SUBB_F_ : ALUarith<0b011, "subb.f", sube, i32lo16z, i32hi16>;
444 [(set i8:$rd, (sube i8:$src, i8:$rr)),455 [(set i16:$rd, (sube i16:$src, i16:$rr)),462 [(set i8:$rd, (sube i8:$src, imm:$k)),471 [(set i16:$rd, (sube i16:$src, imm:$rr)),
478 [(set i8:$rd, (sube i8:$src, i8:$rr)),489 [(set i16:$rd, (sube i16:$src, i16:$rr)),496 [(set i8:$rd, (sube i8:$src, imm:$k)),505 [(set i16:$rd, (sube i16:$src, imm:$rr)),
541 [(set i64:$rT, (sube i64:$rB, i64:$rA))]>;544 [(set i64:$rT, (sube -1, i64:$rA))]>;547 [(set i64:$rT, (sube 0, i64:$rA))]>;
2515 [(set i32:$rT, (sube i32:$rB, i32:$rA))]>;2518 [(set i32:$rT, (sube -1, i32:$rA))]>;2521 [(set i32:$rT, (sube 0, i32:$rA))]>;
992 def SLBR : BinaryRRE<"slb", 0xB999, sube, GR32, GR32>;993 def SLBGR : BinaryRRE<"slbg", 0xB989, sube, GR64, GR64>;996 def SLB : BinaryRXY<"slb", 0xE399, sube, GR32, load, 4>;997 def SLBG : BinaryRXY<"slbg", 0xE389, sube, GR64, load, 8>;
590 [(set i64:$rT, (sube i64:$rB, i64:$rA))]>;593 [(set i64:$rT, (sube -1, i64:$rA))]>;596 [(set i64:$rT, (sube 0, i64:$rA))]>;
330 def SubCCCV4I32 : VecBinaryOp<V4AsmStr<"subc.cc.s32">, sube, V4I32Regs,332 def SubCCCV2I32 : VecBinaryOp<V2AsmStr<"subc.cc.s32">, sube, V2I32Regs,
262 // def EvenOdd : RegisterTuples<[sube, subo], [(add R0, R2), (add R1, R3)]>;266 // let SubRegIndices = [sube, subo] in {
397 def sube : SDNode<"ISD::SUBE" , SDTIntBinOp,
786 void sube(Register dst, Register src1, Register src2, OEBit s = LeaveOE,
821 void Assembler::sube(Register dst, Register src1, Register src2, OEBit o, in sube() function in v8::internal::Assembler
335 // def EvenOdd : RegisterTuples<[sube, subo], [(add R0, R2), (add R1, R3)]>;339 // let SubRegIndices = [sube, subo] in {
375 def sube : SDNode<"ISD::SUBE" , SDTIntBinOp,
359 [(set i32:$sdst, (sube (i32 SSrc_b32:$src0), (i32 SSrc_b32:$src1)))]>;
1198 [(set tGPR:$Rdn, (sube tGPR:$Rn, tGPR:$Rm))]>,
719 defm SUBE : F3_12 <"subxcc" , 0b011100, sube, IntRegs, i32, simm13Op>;
715 defm SUBE : F3_12 <"subxcc" , 0b011100, sube, IntRegs, i32, simm13Op>;