| /external/swiftshader/third_party/llvm-7.0/llvm/test/CodeGen/AArch64/ |
| D | arm64-vsub.ll | 33 ;CHECK-NEXT: subhn2.16b
43 ;CHECK-NEXT: subhn2.8h
53 ;CHECK-NEXT: subhn2.4s
|
| D | arm64-vadd.ll | 909 ;CHECK: subhn2.16b
921 ;CHECK: subhn2.8h
933 ;CHECK: subhn2.4s
|
| D | arm64-neon-3vdiff.ll | 871 ; CHECK: subhn2 {{v[0-9]+}}.16b, {{v[0-9]+}}.8h, {{v[0-9]+}}.8h
885 ; CHECK: subhn2 {{v[0-9]+}}.8h, {{v[0-9]+}}.4s, {{v[0-9]+}}.4s
899 ; CHECK: subhn2 {{v[0-9]+}}.4s, {{v[0-9]+}}.2d, {{v[0-9]+}}.2d
913 ; CHECK: subhn2 {{v[0-9]+}}.16b, {{v[0-9]+}}.8h, {{v[0-9]+}}.8h
927 ; CHECK: subhn2 {{v[0-9]+}}.8h, {{v[0-9]+}}.4s, {{v[0-9]+}}.4s
941 ; CHECK: subhn2 {{v[0-9]+}}.4s, {{v[0-9]+}}.2d, {{v[0-9]+}}.2d
|
| /external/llvm/test/CodeGen/AArch64/ |
| D | arm64-vsub.ll | 33 ;CHECK-NEXT: subhn2.16b
43 ;CHECK-NEXT: subhn2.8h
53 ;CHECK-NEXT: subhn2.4s
|
| D | arm64-vadd.ll | 909 ;CHECK: subhn2.16b
921 ;CHECK: subhn2.8h
933 ;CHECK: subhn2.4s
|
| D | arm64-neon-3vdiff.ll | 871 ; CHECK: subhn2 {{v[0-9]+}}.16b, {{v[0-9]+}}.8h, {{v[0-9]+}}.8h
885 ; CHECK: subhn2 {{v[0-9]+}}.8h, {{v[0-9]+}}.4s, {{v[0-9]+}}.4s
899 ; CHECK: subhn2 {{v[0-9]+}}.4s, {{v[0-9]+}}.2d, {{v[0-9]+}}.2d
913 ; CHECK: subhn2 {{v[0-9]+}}.16b, {{v[0-9]+}}.8h, {{v[0-9]+}}.8h
927 ; CHECK: subhn2 {{v[0-9]+}}.8h, {{v[0-9]+}}.4s, {{v[0-9]+}}.4s
941 ; CHECK: subhn2 {{v[0-9]+}}.4s, {{v[0-9]+}}.2d, {{v[0-9]+}}.2d
|
| /external/v8/src/codegen/arm64/ |
| D | macro-assembler-arm64.h | 440 V(subhn2, Subhn2) \
|
| D | assembler-arm64.h | 1143 void subhn2(const VRegister& vd, const VRegister& vn, const VRegister& vm);
|
| D | assembler-arm64.cc | 1505 V(subhn2, NEON_SUBHN2, vd.IsQ()) \
|
| /external/v8/src/execution/arm64/ |
| D | simulator-arm64.h | 1982 V(subhn2) \
|
| D | simulator-arm64.cc | 4359 subhn2(vf, rd, rn, rm); in VisitNEON3Different()
|
| D | simulator-logic-arm64.cc | 2799 LogicVRegister Simulator::subhn2(VectorFormat vform, LogicVRegister dst, in subhn2() function in v8::internal::Simulator
|
| /external/vixl/test/test-trace-reference/ |
| D | log-disasm | 1778 0x~~~~~~~~~~~~~~~~ 4e2960cb subhn2 v11.16b, v6.8h, v9.8h
1779 0x~~~~~~~~~~~~~~~~ 4eb86259 subhn2 v25.4s, v18.2d, v24.2d
1780 0x~~~~~~~~~~~~~~~~ 4e6162b4 subhn2 v20.8h, v21.4s, v1.4s
|
| D | log-disasm-colour | 1778 0x~~~~~~~~~~~~~~~~ 4e2960cb subhn2 v11.16b, v6.8h, v9.8h
1779 0x~~~~~~~~~~~~~~~~ 4eb86259 subhn2 v25.4s, v18.2d, v24.2d
1780 0x~~~~~~~~~~~~~~~~ 4e6162b4 subhn2 v20.8h, v21.4s, v1.4s
|
| D | log-cpufeatures-custom | 1777 0x~~~~~~~~~~~~~~~~ 4e2960cb subhn2 v11.16b, v6.8h, v9.8h ### {NEON} ###
1778 0x~~~~~~~~~~~~~~~~ 4eb86259 subhn2 v25.4s, v18.2d, v24.2d ### {NEON} ###
1779 0x~~~~~~~~~~~~~~~~ 4e6162b4 subhn2 v20.8h, v21.4s, v1.4s ### {NEON} ###
|
| D | log-cpufeatures | 1777 0x~~~~~~~~~~~~~~~~ 4e2960cb subhn2 v11.16b, v6.8h, v9.8h // Needs: NEON
1778 0x~~~~~~~~~~~~~~~~ 4eb86259 subhn2 v25.4s, v18.2d, v24.2d // Needs: NEON
1779 0x~~~~~~~~~~~~~~~~ 4e6162b4 subhn2 v20.8h, v21.4s, v1.4s // Needs: NEON
|
| D | log-cpufeatures-colour | 1777 0x~~~~~~~~~~~~~~~~ 4e2960cb subhn2 v11.16b, v6.8h, v9.8h [1;35mNEON[0;m
1778 0x~~~~~~~~~~~~~~~~ 4eb86259 subhn2 v25.4s, v18.2d, v24.2d [1;35mNEON[0;m
1779 0x~~~~~~~~~~~~~~~~ 4e6162b4 subhn2 v20.8h, v21.4s, v1.4s [1;35mNEON[0;m
|
| D | log-all | 4859 0x~~~~~~~~~~~~~~~~ 4e2960cb subhn2 v11.16b, v6.8h, v9.8h
4861 0x~~~~~~~~~~~~~~~~ 4eb86259 subhn2 v25.4s, v18.2d, v24.2d
4863 0x~~~~~~~~~~~~~~~~ 4e6162b4 subhn2 v20.8h, v21.4s, v1.4s
|
| /external/vixl/test/aarch64/ |
| D | test-trace-aarch64.cc | 2115 __ subhn2(v11.V16B(), v6.V8H(), v9.V8H()); in GenerateTestSequenceNEON() local
2116 __ subhn2(v25.V4S(), v18.V2D(), v24.V2D()); in GenerateTestSequenceNEON() local
2117 __ subhn2(v20.V8H(), v21.V4S(), v1.V4S()); in GenerateTestSequenceNEON() local
|
| D | test-cpu-features-aarch64.cc | 2380 TEST_NEON(subhn2_0, subhn2(v0.V16B(), v1.V8H(), v2.V8H()))
2381 TEST_NEON(subhn2_1, subhn2(v0.V8H(), v1.V4S(), v2.V4S()))
2382 TEST_NEON(subhn2_2, subhn2(v0.V4S(), v1.V2D(), v2.V2D()))
|
| /external/vixl/src/aarch64/ |
| D | simulator-aarch64.h | 2845 V(subhn2) \
|
| D | assembler-aarch64.h | 3459 void subhn2(const VRegister& vd, const VRegister& vn, const VRegister& vm);
|
| D | macro-assembler-aarch64.h | 2706 V(subhn2, Subhn2) \
|
| D | simulator-aarch64.cc | 4990 subhn2(vf, rd, rn, rm); in VisitNEON3Different()
|
| D | logic-aarch64.cc | 3530 LogicVRegister Simulator::subhn2(VectorFormat vform, in subhn2() function in vixl::aarch64::Simulator
|