Home
last modified time | relevance | path

Searched refs:subop (Results 1 – 8 of 8) sorted by relevance

/external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/ARC/
DARCInstrFormats.td197 // |B[2-0] | 0| 0| 1| 0| 1| 1| 1| 1| F|B[5-3] |C |subop |
198 class F32_SOP_RR<bits<5> major, bits<6> subop, bit F, dag outs, dag ins,
212 let Inst{5-0} = subop;
220 // |B[2-0] | 0| 0| subop| F|B[5-3] |C |A |
221 class F32_DOP_RR<bits<5> major, bits<6> subop, bit F, dag outs, dag ins,
231 let Inst{21-16} = subop;
241 // |B[2-0] | 1| 1| subop| F|B[5-3] |C |A |
242 class F32_DOP_CC_RR<bits<5> major, bits<6> subop, bit F, dag outs, dag ins,
252 let Inst{21-16} = subop;
263 // |B[2-0] | 0| 1| subop| F|B[5-3] |U6 |A |
[all …]
DARCInstrInfo.td175 multiclass ArcSpecialDOPInst<bits<6> subop, string opasm, bit F> {
176 def _rr : F32_DOP_RR<0b00100, subop, F, (outs), (ins GPR32:$B, GPR32:$C),
180 def _ru6 : F32_DOP_RU6<0b00100, subop, F, (outs), (ins GPR32:$B, i32imm:$U6),
184 def _rlimm : F32_DOP_RLIMM<0b00100, subop, F, (outs),
191 multiclass ArcUnaryInst<bits<5> major, bits<6> subop,
193 def _rr : F32_SOP_RR<major, subop, 0, (outs GPR32:$B), (ins GPR32:$C),
196 def _f_rr : F32_SOP_RR<major, subop, 1, (outs GPR32:$B), (ins GPR32:$C),
/external/mesa3d/src/gallium/drivers/nouveau/codegen/
Dnv50_ir_emit_gv100.cpp247 int subop = 0; in emitFRND() local
252 case ROUND_NI: subop = 0; break; in emitFRND()
253 case ROUND_MI: subop = 1; break; in emitFRND()
254 case ROUND_PI: subop = 2; break; in emitFRND()
255 case ROUND_ZI: subop = 3; break; in emitFRND()
261 case OP_FLOOR: subop = 1; break; in emitFRND()
262 case OP_CEIL : subop = 2; break; in emitFRND()
263 case OP_TRUNC: subop = 3; break; in emitFRND()
275 emitField(78, 2, subop); in emitFRND()
1516 uint8_t subop, redop = 0x00; in emitBAR() local
[all …]
Dnv50_ir_emit_gm107.cpp3155 uint8_t subop; in emitBAR() local
3160 case NV50_IR_SUBOP_BAR_RED_POPC: subop = 0x02; break; in emitBAR()
3161 case NV50_IR_SUBOP_BAR_RED_AND: subop = 0x0a; break; in emitBAR()
3162 case NV50_IR_SUBOP_BAR_RED_OR: subop = 0x12; break; in emitBAR()
3163 case NV50_IR_SUBOP_BAR_ARRIVE: subop = 0x81; break; in emitBAR()
3165 subop = 0x80; in emitBAR()
3170 emitField(0x20, 8, subop); in emitBAR()
/external/one-true-awk/
Dawkgram.y73 %type <i> subop print
348 subop:
404 | subop '(' reg_expr comma pattern ')'
406 | subop '(' pattern comma pattern ')'
411 | subop '(' reg_expr comma pattern comma var ')'
413 | subop '(' pattern comma pattern comma var ')'
/external/mesa3d/docs/relnotes/
D10.1.5.rst58 - nv50/ir: fix constant folding for OP_MUL subop HIGH
D10.1.6.rst104 - nv50/ir: clear subop when folding constant expressions
/external/tensorflow/tensorflow/compiler/jit/
Ddeadness_analysis.cc693 for (Predicate* subop : op->GetOperands()) { in MakeAndOrImpl()
694 if (simplified_ops_set.insert(subop).second) { in MakeAndOrImpl()
695 simplified_ops.push_back(subop); in MakeAndOrImpl()