Searched refs:subphy_id (Results 1 – 3 of 3) sorted by relevance
| /external/u-boot/drivers/ddr/marvell/a38x/ |
| D | ddr3_training_leveling.c | 1681 int i, subphy_id, step; in mv_ddr_rl_dqs_burst() local
1717 for (subphy_id = 0; subphy_id < MAX_BUS_NUM; subphy_id++) in mv_ddr_rl_dqs_burst()
1719 if (IS_BUS_ACTIVE(tm->bus_act_mask, subphy_id) == 0) in mv_ddr_rl_dqs_burst()
1783 for (subphy_id = 0; subphy_id < MAX_BUS_NUM; subphy_id++) { in mv_ddr_rl_dqs_burst()
1784 if (rl_state[effective_cs][subphy_id][if_id] == RL_BEHIND) in mv_ddr_rl_dqs_burst()
1786 ddr3_tip_bus_read(dev_num, if_id, ACCESS_TYPE_UNICAST, subphy_id, DDR_PHY_DATA, in mv_ddr_rl_dqs_burst()
1788 ddr3_tip_bus_read(dev_num, if_id, ACCESS_TYPE_UNICAST, subphy_id, DDR_PHY_DATA, in mv_ddr_rl_dqs_burst()
1792 __func__, effective_cs, i, subphy_id, in mv_ddr_rl_dqs_burst()
1793 rl_state[effective_cs][subphy_id][if_id], in mv_ddr_rl_dqs_burst()
1796 switch (rl_state[effective_cs][subphy_id][if_id]) { in mv_ddr_rl_dqs_burst()
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| D | ddr3_training_ip_engine.h | 77 u8 mv_ddr_tip_sub_phy_byte_status_get(u32 if_id, u32 subphy_id);
78 void mv_ddr_tip_sub_phy_byte_status_set(u32 if_id, u32 subphy_id, u8 byte_status_data);
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| D | ddr3_training_ip_engine.c | 1445 u8 mv_ddr_tip_sub_phy_byte_status_get(u32 if_id, u32 subphy_id) in mv_ddr_tip_sub_phy_byte_status_get() argument
1447 return byte_status[if_id][subphy_id]; in mv_ddr_tip_sub_phy_byte_status_get()
1450 void mv_ddr_tip_sub_phy_byte_status_set(u32 if_id, u32 subphy_id, u8 byte_status_data) in mv_ddr_tip_sub_phy_byte_status_set() argument
1452 byte_status[if_id][subphy_id] = byte_status_data; in mv_ddr_tip_sub_phy_byte_status_set()
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