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Searched refs:surface_count (Results 1 – 10 of 10) sorted by relevance

/external/igt-gpu-tools/tests/
Deviction_common.c134 uint64_t surface_count) in mlocked_evictions() argument
139 intel_require_memory(surface_count, surface_size, CHECK_RAM); in mlocked_evictions()
146 sz = surface_size * surface_count; in mlocked_evictions()
155 bo = malloc(surface_count * sizeof(*bo)); in mlocked_evictions()
157 lock -= ALIGN(surface_count * sizeof(*bo), 4096); in mlocked_evictions()
165 for (n = 0; n < surface_count; n++) in mlocked_evictions()
168 for (n = 0; n < surface_count - 2; n++) { in mlocked_evictions()
169 igt_permute_array(bo, surface_count, exchange_uint32_t); in mlocked_evictions()
170 ret = ops->copy(fd, bo[0], bo[1], bo, surface_count-n); in mlocked_evictions()
185 for (n = 0; n < surface_count; n++) in mlocked_evictions()
/external/crosvm/gpu_renderer/src/
Dcommand_buffer.rs125 fn cmd_set_fb_state_size(surface_count: u32) -> u32 { in e_set_fb_state()
126 2 + surface_count in e_set_fb_state()
/external/mesa3d/src/intel/vulkan/
Danv_nir_apply_pipeline_layout.c1191 map->surface_to_descriptor[map->surface_count] = in anv_nir_apply_pipeline_layout()
1196 state.set[s].desc_offset = map->surface_count; in anv_nir_apply_pipeline_layout()
1197 map->surface_count++; in anv_nir_apply_pipeline_layout()
1202 state.constants_offset = map->surface_count; in anv_nir_apply_pipeline_layout()
1203 map->surface_to_descriptor[map->surface_count].set = in anv_nir_apply_pipeline_layout()
1205 map->surface_count++; in anv_nir_apply_pipeline_layout()
1272 if (map->surface_count + array_size > MAX_BINDING_TABLE_SIZE || in anv_nir_apply_pipeline_layout()
1280 state.set[set].surface_offsets[b] = map->surface_count; in anv_nir_apply_pipeline_layout()
1286 map->surface_to_descriptor[map->surface_count++] = in anv_nir_apply_pipeline_layout()
1296 map->surface_to_descriptor[map->surface_count++] = in anv_nir_apply_pipeline_layout()
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Danv_pipeline_cache.c64 bind_map->surface_count); in anv_shader_bin_create()
127 bind_map->surface_count); in anv_shader_bin_create()
182 blob_write_uint32(blob, shader->bind_map.surface_count); in anv_shader_bin_write_to_blob()
185 shader->bind_map.surface_count * in anv_shader_bin_write_to_blob()
233 bind_map.surface_count = blob_read_uint32(blob); in anv_shader_bin_create_from_blob()
236 blob_read_bytes(blob, bind_map.surface_count * in anv_shader_bin_create_from_blob()
DgenX_pipeline.c1132 uint32_t surface_count = 0; local
1136 surface_count = map->surface_count;
1140 GENX(BLEND_STATE_ENTRY_length) * surface_count;
1150 for (unsigned i = 0; i < surface_count; i++) {
1569 return DIV_ROUND_UP(bin->bind_map.surface_count, 32);
1883 for (int i = 0; i < bind_map->surface_count; i++) {
2432 .BindingTableEntryCount = 1 + MIN2(cs_bin->bind_map.surface_count, 30),
Danv_descriptor_set.c250 uint32_t surface_count[MESA_SHADER_STAGES] = { 0, }; in anv_GetDescriptorSetLayoutSupport() local
294 surface_count[s] += sampler->n_planes; in anv_GetDescriptorSetLayoutSupport()
298 surface_count[s] += binding->descriptorCount; in anv_GetDescriptorSetLayoutSupport()
307 surface_count[s] += binding->descriptorCount; in anv_GetDescriptorSetLayoutSupport()
314 surface_count[s] += 1; in anv_GetDescriptorSetLayoutSupport()
335 if (surface_count[s] > MAX_BINDING_TABLE_SIZE - MAX_RTS) in anv_GetDescriptorSetLayoutSupport()
Danv_pipeline.c1011 assert(stage->bind_map.surface_count == 0); in anv_pipeline_link_fs()
1014 stage->bind_map.surface_count += num_rt_bindings; in anv_pipeline_link_fs()
1731 stage.bind_map.surface_count = 1; in anv_pipeline_compile_cs()
DgenX_cmd_buffer.c2548 if (map->surface_count == 0) { in emit_binding_table()
2554 map->surface_count, in emit_binding_table()
2568 for (uint32_t s = 0; s < map->surface_count; s++) { in emit_binding_table()
Danv_blorp.c68 .surface_count = 0, in upload_blorp_shader()
Danv_private.h3341 uint32_t surface_count; member